TCS Pune

NM-D552 – Bench Power & Signal Checklist

Board-specific bench checklist derived from supplied schematic source(s) for NM-D552 Rev 2. Only signals confidently located in the supplied source were added; undocumented thresholds remain technician-verified rather than guessed.

V4.7 · REVISION SAFETY

NM-D552 · Rev 2

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

I verified the physical board revision is Rev 2.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 NM-D552Expert⏱ 60-180 minutes📋 5 steps

Compatible models: Lenovo Thor-P Gen2 platform

⚠ Safety: Disconnect battery/AC before resistance or diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify exact board/revision before using reference values.

🛠 Required Tools

Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required

0 / 5 done

1Confirm board identity and fault conditionRecord exact board code/revision, symptom, adapter/battery condition and current power state before measurements.⚠ Use the exact board revision; similar boards can use different rails, ICs or sequencing.
2Unpowered resistance / short checkWith all power removed, check input, always-on, memory and CPU/GPU rails for abnormal resistance before any injection.⚠ Low resistance on core rails can be normal. Never inject until safe voltage/current limits and topology are confirmed.
3Trace the chronological power sequenceFollow the board-specific rows in order and stop at the first missing prerequisite.⚠ A missing downstream signal is often a consequence, not the root cause.
4Capture dynamic signals where requiredUse a x10 probe and short ground connection for reset, SPI, PWM, CC/PD, eDP AUX and other dynamic signals.⚠ Avoid long probe ground leads on switching/high-speed nodes.
5Record repair and complete final QCAfter repair, repeat the failed stage and complete V5.9 final QC before marking solved.⚠ Do not publish solved until the original symptom is reproducibly cleared.

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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): NM-D552.pdf

Board profile

Power & Control Architecture

Platform / ODMLCFC Thor-P Gen2 (PCB NM-D552 Rev2; schematic doc 0.3)

CPU / SoCIntel Tiger Lake

MemoryDDR5

EC / SIONPCX997

ChargerRT4501

BIOS / SPIMX25L25673GM2I-

Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#	Stage	Signal / Rail	From -> To	Ref	State	Expected	DMM	Oscilloscope
1	ATX / Standby	PS_ON#	SIO/PCH -> PSU enable	NM-D552 schematic p.16	Follow chronological sequence	Board-specific active-low PSU enable transition.	Observe idle and power-on transition.	Clean assertion/deassertion.
2	ATX / Standby	ATX PWR_OK	PSU -> board power-good	NM-D552 schematic p.14	Follow chronological sequence	Valid PSU power-good after main rails stabilize.	Measure logic transition after PS_ON#.	Clean assertion after stable rails.
3	Main Rails	+3.3V system rail	System 3.3 V rail	NM-D552 schematic p.25	Follow chronological sequence	Nominal 3.3 V-class system rail.	Measure at regulator/output test point.	Stable DC.
4	DC Input	Adapter / DC-IN main rail	Input connector / protection path	NM-D552 schematic p.1	Follow chronological sequence	Board-specific adapter/input voltage; verify adapter or USB-C contract and schematic.	Measure DC to ground at the input/protection path.	Flat DC; investigate collapse or excessive ripple.
5	Charger	ACDET	Adapter detect -> charger	NM-D552 schematic p.102	Follow chronological sequence	Board/charger-IC specific adapter-detect level.	Measure ACDET against charger datasheet/schematic.	Stable qualification level after adapter insertion.
6	Charger	ACOK / ACIN	Charger -> EC/SMC	NM-D552 schematic p.30	Follow chronological sequence	Valid adapter-present logic state; polarity is board/IC specific.	Measure logic level and insertion/removal transition.	Clean state transition.
7	Always-On	3V always-on / S5 rail	Always-on 3V rail	NM-D552 schematic p.105	Follow chronological sequence	Nominal board-specific 3V-class always-on rail.	Measure at regulator output coil/capacitor.	Clean startup and stable DC.
8	EC / SMC	EC / KBC / SMC supply	EC/KBC/SMC power	NM-D552 schematic p.1	Follow chronological sequence	Controller supply must be valid before sequence outputs are expected.	Measure controller supply rail(s).	Flat DC; no repeated collapse.
9	EC / SMC	32.768 kHz RTC / EC clock	RTC / EC low-frequency clock	NM-D552 schematic p.15	Follow chronological sequence	Stable low-frequency oscillation where applicable.	Use high-impedance scope probe; avoid loading crystal nodes.	~32.768 kHz waveform where exposed.
10	Reset	RSMRST#	EC/PCH reset sequence	NM-D552 schematic p.15	Follow chronological sequence	Board-specific deasserted state after resume-well prerequisites.	Measure logic state through power transition.	Clean assertion/deassertion.
11	Power Button	PWRBTN#	Button/EC -> PCH/SoC	NM-D552 schematic p.14	Follow chronological sequence	Valid board-specific button transition when pressed.	Observe idle and pressed state.	Clean pulse/transition.
12	Sleep / Sequence	SLP_S5#	PCH/SoC -> power sequencing	NM-D552 schematic p.14	Follow chronological sequence	Board-specific deassertion when leaving S5.	Measure during power-on sequence.	Clean transition.
13	Sleep / Sequence	SLP_S4#	PCH/SoC -> power sequencing	NM-D552 schematic p.4	Follow chronological sequence	Board-specific deassertion when leaving S4.	Measure during power-on sequence.	Clean transition.
14	Sleep / Sequence	SLP_S3#	PCH/SoC -> main rails	NM-D552 schematic p.4	Follow chronological sequence	Board-specific deassertion when entering S0.	Measure during power-on sequence.	Clean transition.
15	Power Good	SUS_PWRGD	Suspend rails -> logic	NM-D552 schematic p.4	Follow chronological sequence	Valid suspend-power-good state after required rails stabilize.	Measure after always-on/suspend rails.	Clean assertion.
16	VR Enable	VR_ON / VR enable	EC/PCH -> VR controller	NM-D552 schematic p.47	Follow chronological sequence	Board-specific VR enable state.	Measure at VR controller enable pin/path.	Clean assertion before core rail rise.
17	CPU / SoC VR	VCORE / CPU core rail	CPU/SoC core VR output	NM-D552 schematic p.11	Follow chronological sequence	Dynamic low-voltage core rail; exact value depends on CPU state.	Measure at core inductors with suitable meter/scope.	Controlled ramp; switching activity under load.
18	Power Good	SYS_PWROK / ALL_SYS_PWRGD	System power-good chain	NM-D552 schematic p.15	Follow chronological sequence	Valid board-specific power-good after required rails are stable.	Measure logic state after main rails rise.	Clean assertion.
19	Reset	PLTRST#	PCH/SoC -> platform devices	NM-D552 schematic p.8	Follow chronological sequence	Deasserted platform reset after clocks, rails and power-good prerequisites.	Measure during startup.	Clean reset release.
20	BIOS / SPI	SPI chip select	Controller -> SPI flash	NM-D552 schematic p.15	Follow chronological sequence	Idle/inactive with access pulses during firmware fetch.	Scope during power-on/reset release.	Chip-select pulse bursts.
21	BIOS / SPI	SPI clock	Controller -> SPI flash	NM-D552 schematic p.13	Follow chronological sequence	Clock bursts during flash access.	Scope during firmware access.	High-frequency clock bursts.
22	Display	LCD / eDP panel power	Panel power path	NM-D552 schematic p.16	Follow chronological sequence	Board-specific panel logic supply from schematic.	Measure at panel fuse/load switch/connector.	Stable DC after panel enable.
23	Display	eDP HPD	Panel -> GPU/PCH/SoC	NM-D552 schematic p.2	Follow chronological sequence	Valid board-specific HPD state when panel is detected.	Measure with panel connected and powered.	Clean logic level/transition.
24	Display	eDP AUX	GPU/PCH/SoC panel	NM-D552 schematic p.8	Follow chronological sequence	AUX transactions during panel detection/EDID/link setup.	Use suitable scope/differential method; avoid loading the bus.	Bidirectional AUX activity.
25	Display	Backlight PWM	EC/PCH/GPU -> backlight	NM-D552 schematic p.44	Follow chronological sequence	PWM activity when brightness is nonzero; exact duty/frequency is platform specific.	Scope PWM and record duty/frequency.	Stable PWM waveform.
26	Battery / Bus	SMBus / I2C activity	EC/charger/battery bus	NM-D552 schematic p.3	Follow chronological sequence	Pulled-high idle with transaction bursts when devices are queried.	Scope clock/data and confirm pull-up rail.	I2C/SMBus clock/data bursts.
27	USB-C / PD	USB-C CC1 / CC2	USB-C port -> PD controller	NM-D552 schematic p.1	Follow chronological sequence	Valid attachment/orientation state; exact voltage depends on Rp/Rd and role.	Measure CC states according to controller datasheet and port orientation.	Observe attach/orientation changes.
28	USB-C / PD	PD negotiation / contract	USB-C PD controller	NM-D552 schematic p.1	Follow chronological sequence	Contract may be 5/9/15/20 V or PPS depending platform/source.	Verify default VBUS first, then observe negotiation and final contract.	PD communication / VBUS transition when negotiation succeeds.

Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 28 checked

Checked	#	Signal / Rail	Failure Isolation Hint	Technician Notes
Checked	1	PS_ON#NM-D552 schematic p.16	No PS_ON#: check standby rails, SIO/EC state, power button and reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	2	ATX PWR_OKNM-D552 schematic p.14	Missing PWR_OK: inspect PSU/main rails and excessive load. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	3	+3.3V system railNM-D552 schematic p.25	Missing: inspect source enable, regulator input and load. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	4	Adapter / DC-IN main railNM-D552 schematic p.1	No input: inspect source, connector, fuse/protection path and system-rail short. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	5	ACDETNM-D552 schematic p.102	Abnormal ACDET: inspect divider, charger VCC, source and surrounding passives. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	6	ACOK / ACINNM-D552 schematic p.30	Missing: verify charger VCC, ACDET, source qualification and pull-up rail. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	7	3V always-on / S5 railNM-D552 schematic p.105	Missing: inspect regulator input/enable, shorted load and prerequisite power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	8	EC / KBC / SMC supplyNM-D552 schematic p.1	Missing/unstable controller supply blocks power-button and sequencing logic. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	9	32.768 kHz RTC / EC clockNM-D552 schematic p.15	Absent clock: verify oscillator supply, crystal network and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	10	RSMRST#NM-D552 schematic p.15	Missing: check RTC/resume-well rails, EC/SMC state and upstream power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	11	PWRBTN#NM-D552 schematic p.14	No transition: inspect button, EC path, pull-up and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	12	SLP_S5#NM-D552 schematic p.14	Missing: diagnose upstream reset/firmware/power prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	13	SLP_S4#NM-D552 schematic p.4	Missing: inspect prior sleep/reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	14	SLP_S3#NM-D552 schematic p.4	Missing: inspect prior sleep/reset/firmware prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	15	SUS_PWRGDNM-D552 schematic p.4	Missing: verify rail regulation and upstream enables. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	16	VR_ON / VR enableNM-D552 schematic p.47	Missing: inspect sleep signals, EC/PCH outputs and interlocks. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	17	VCORE / CPU core railNM-D552 schematic p.11	Missing: inspect VR enable, controller supply, phases and SVID/control prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	18	SYS_PWROK / ALL_SYS_PWRGDNM-D552 schematic p.15	Missing: find the first upstream rail or PGOOD that is absent. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	19	PLTRST#NM-D552 schematic p.8	Missing: trace SYS_PWROK/VR_PWRGD/VR enable/sleep/reset prerequisites first. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	20	SPI chip selectNM-D552 schematic p.15	No activity: verify sequence reached firmware fetch before suspecting the flash. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	21	SPI clockNM-D552 schematic p.13	CS without clock suggests bus/controller path; no bus activity may be upstream sequence. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	22	LCD / eDP panel powerNM-D552 schematic p.16	Missing: inspect panel enable, fuse/load switch, shorted cable/panel and display prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	23	eDP HPDNM-D552 schematic p.2	Missing: inspect panel power, cable/connector and HPD path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	24	eDP AUXNM-D552 schematic p.8	No AUX with power/HPD valid: inspect cable, panel and source path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	25	Backlight PWMNM-D552 schematic p.44	Missing PWM with enable present: inspect brightness-control source and firmware/EC path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	26	SMBus / I2C activityNM-D552 schematic p.3	Stuck/no activity: inspect pull-ups, shorts and powered bus participants. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	27	USB-C CC1 / CC2NM-D552 schematic p.1	Abnormal state: inspect connector, ESD/protection, pull networks and controller supply. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	28	PD negotiation / contractNM-D552 schematic p.1	No contract: verify CC state, controller supply, dead-battery path, firmware and cable/source compatibility. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence

V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet

Adapter connectedANo successful-repair baseline yet

StandbyANo successful-repair baseline yet

Power-button pressANo successful-repair baseline yet

CPU initializationANo successful-repair baseline yet

BIOS activityANo successful-repair baseline yet

POSTANo successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for NM-D552.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

REFERENCE BOARD