TCS Pune

LA-K092P – Bench Power & Signal Checklist

Board-specific bench checklist derived from supplied schematic source(s) for LA-K092P 2A. Only signals located in the supplied schematic text were added automatically; missing thresholds or values remain technician-verified rather than guessed.

V4.7 · REVISION SAFETY

LA-K092P · Rev 2A

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

I verified the physical board revision is Rev 2A.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 LA-K092PExpert⏱ 60-180 minutes📋 5 steps

Compatible models: Acer Aspire AV15-51; FH7AT/FH5AT/FH4AT

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify board/revision before using reference values.

🛠 Required Tools

Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required

0 / 5 done

1Confirm board identity and fault conditionRecord the exact board code/revision, reported symptom, adapter/battery condition and present power state before measurements.⚠ Use the exact board revision; similar board codes may use different power ICs, rail names or sequencing.
2Unpowered resistance / short checkWith all power removed, check the main input, always-on rails, memory rails and CPU/GPU rails for abnormal resistance to ground before power injection.⚠ Low resistance on CPU/GPU core rails can be normal. Never inject voltage until the rail topology and safe voltage/current limit are confirmed.
3Trace the chronological power sequenceFollow the board-specific bench rows in order. Stop at the first missing prerequisite and diagnose upstream before moving downstream.⚠ A missing downstream signal is often a consequence, not the root cause.
4Capture dynamic signals where requiredUse a x10 probe and short ground connection for reset, SPI, PWM, CC/PD, eDP AUX and other dynamic signals.⚠ Avoid long probe ground leads on switching nodes and high-speed buses.
5Record repair and verify all functionsAfter repair, repeat the failed stage and complete final QC including charging, display, ports, thermal/load behavior, sleep/wake and multiple cold boots.⚠ Do not mark solved until the original symptom is reproducibly cleared and V5.9 QC passes.

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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): Acer Aspire AV15-51 Compal LA-K092P r2A.pdf

Board profile

Power & Control Architecture

Platform / ODMCompal

CPU / SoCIntel Tiger Lake

PCH / ChipsetTiger Lake PCH-LP

MemoryDDR4

EC / SIOKB9052 family

ChargerBQ24781

CPU VRRT3612EB

Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#	Stage	Signal / Rail	From -> To	Ref	State	Expected	DMM	Oscilloscope
1	DC Input	Adapter / DC-IN main rail	Input connector / protection path	Schematic p.3	Follow chronological sequence	Board-specific adapter/input voltage; verify source/PD contract and schematic.	Measure DC to ground at the adapter/input protection path.	Flat DC; investigate collapse or excessive ripple.
2	Charger	ACDET	Charger adapter-detect divider	Schematic p.82	Follow chronological sequence	Must be within the charger IC valid adapter-detect window; verify charger datasheet and divider.	Measure DC at ACDET.	Stable analog level after adapter insertion.
3	Charger	ACOK / ACIN	Charger -> EC/SMC	Schematic p.5	Follow chronological sequence	Valid adapter-present logic state when the source is accepted; polarity is board/IC specific.	Measure logic level and observe insertion/removal transition.	Clean state transition on adapter insertion/removal.
4	Charger	REGN / charger LDO	Charger internal regulator	Schematic p.84	Follow chronological sequence	IC-specific internal LDO voltage; use the exact charger datasheet.	Measure at REGN pin/capacitor.	Flat DC.
5	Always-On	3V always-on / S5 rail	Always-on 3V rail	Schematic p.3	Follow chronological sequence	Nominal rail voltage indicated by schematic rail name; verify tolerance from source.	Measure at rail coil/capacitor to ground.	Clean startup and stable DC.
6	Always-On	5V always-on / S5 rail	Always-on 5V rail	Schematic p.3	Follow chronological sequence	Nominal rail voltage indicated by schematic rail name; verify tolerance from source.	Measure at rail coil/capacitor to ground.	Clean startup and stable DC.
7	EC / SMC	EC / SMC supply	EC/KBC/SMC power	Schematic p.5	Follow chronological sequence	Board-specific EC/SMC supply must be valid and stable.	Measure EC/SMC supply rails before expecting sequence outputs.	Flat DC; no repeated collapse.
8	EC / SMC	32.768 kHz RTC / EC clock	RTC / EC low-frequency clock	Schematic p.11	Follow chronological sequence	Stable low-frequency oscillation where the board exposes/measures it.	Oscilloscope with high-impedance probe; avoid loading crystal nodes.	~32.768 kHz waveform when applicable.
9	Reset	RSMRST#	EC/SMC/PCH reset path	Schematic p.5	Follow chronological sequence	Must release only after required standby power/clock conditions are met; polarity by signal suffix.	Measure logic level and transition during standby sequence.	Clean reset release.
10	Power Button	PWRBTN# / power switch	Button -> EC/SMC/PCH	Schematic p.11	Follow chronological sequence	Expected active transition according to board polarity.	Observe logic transition while pressing the button.	Clean pulse on press/release.
11	Sleep State	SLP_S5#	PCH/SoC sleep state	Schematic p.3	Follow chronological sequence	Must transition according to the board power-state sequence.	Measure logic state during attempted power-up.	Clean state transition.
12	Sleep State	SLP_S4#	PCH/SoC sleep state	Schematic p.3	Follow chronological sequence	Must transition according to the board power-state sequence.	Measure logic state during attempted power-up.	Clean state transition.
13	Sleep State	SLP_S3#	PCH/SoC sleep state	Schematic p.3	Follow chronological sequence	Must transition before dependent S0 rails are expected.	Measure logic state during attempted power-up.	Clean state transition.
14	Memory	Memory VDD / VDDQ	Memory power	Schematic p.3	Follow chronological sequence	Nominal board-specific memory rail voltage for installed memory generation.	Measure rail voltage at memory coil/capacitors.	Stable DC with normal ramp.
15	CPU / SoC	VR_ON / CPU VR enable	EC/SMC/SoC -> CPU VR	Schematic p.5	Follow chronological sequence	Board-specific active logic state when CPU core power is requested.	Measure enable logic at VR controller.	Clean assertion before core rail rise.
16	CPU / SoC	CPU VCORE	CPU core regulator output	Schematic p.88	Follow chronological sequence	Dynamic CPU core voltage; exact value depends on platform and operating state.	Measure at CPU core inductor/output capacitors.	Observe controlled ramp; scope ripple if unstable.
17	CPU / SoC	CPU VR power-good / VR_RDY	CPU VR -> platform logic	Schematic p.5	Follow chronological sequence	Asserted only after the VR output is within regulation; exact polarity/name is board specific.	Measure logic after core rail starts.	Clean delayed assertion.
18	CPU / SoC	SVID clock/data	CPU/SoC VR controller	Schematic p.15	Follow chronological sequence	Digital activity during CPU voltage negotiation when supported.	Use oscilloscope; DMM is not diagnostic for bus activity.	Bursting clock/data activity.
19	Power Good	SYS_PWROK / ALL_SYS_PWRGD	Aggregate power-good logic	Schematic p.5	Follow chronological sequence	Asserted only after required platform rails/power-good inputs are valid.	Measure logic after required rails are stable.	Clean delayed assertion.
20	Reset	PLTRST# / platform reset	PCH/SoC -> platform devices	Schematic p.5	Follow chronological sequence	Released only after clocks, firmware and power-good prerequisites are satisfied.	Measure logic level and startup transition.	Clean reset release.
21	BIOS / SPI	BIOS / SPI flash supply	SPI flash supply	Schematic p.9	Follow chronological sequence	Use exact flash marking/datasheet; commonly 1.8 V or 3.3 V but never assume.	Identify exact flash device first, then measure VCC.	Stable DC.
22	BIOS / SPI	SPI chip-select	Controller -> SPI flash	Schematic p.6	Follow chronological sequence	Idle/inactive with access pulses when firmware is being read.	Oscilloscope during power-on/reset release.	Chip-select pulse bursts.
23	BIOS / SPI	SPI clock	Controller -> SPI flash	Schematic p.6	Follow chronological sequence	Clock bursts during flash access.	Oscilloscope during firmware access.	High-frequency clock bursts.
24	Display	LCD / eDP panel power	Panel power switch -> connector	Schematic p.6	Follow chronological sequence	Board-specific panel logic supply as shown in schematic.	Measure at panel connector/fuse/load switch.	Stable DC after panel enable.
25	Display	eDP HPD	Panel -> GPU/PCH/SoC	Schematic p.6	Follow chronological sequence	Valid board-specific HPD state when panel is detected.	Measure HPD logic with panel connected and powered.	Clean logic level/transition.
26	Display	eDP AUX	GPU/PCH/SoC panel	Schematic p.6	Follow chronological sequence	AUX transactions during panel detection/EDID/link setup.	Use oscilloscope/differential method suitable for AUX; avoid loading the bus.	Bidirectional AUX activity during display initialization.
27	Display	Backlight PWM	EC/PCH/GPU -> backlight controller	Schematic p.6	Follow chronological sequence	PWM activity when brightness is nonzero; exact frequency/duty is platform specific.	Use oscilloscope; measure duty/frequency.	Stable PWM waveform.
28	Battery	Battery SMBus	EC/charger battery	Schematic p.3	Follow chronological sequence	Pulled-high idle with transaction bursts when battery is queried.	Use oscilloscope for clock/data activity; confirm pull-up rail.	I2C/SMBus clock/data bursts.
29	USB-C / PD	USB-C CC1 / CC2	USB-C port -> PD controller	Schematic p.16	Follow chronological sequence	Valid CC attachment/orientation state; exact voltage depends on source/sink role and Rp/Rd.	Measure CC states according to Type-C/PD controller datasheet and port orientation.	Observe attach/orientation changes.
30	USB-C / PD	PD negotiation / contract	USB-C PD controller	Schematic p.6	Follow chronological sequence	Contract may be 5/9/15/20 V or PPS depending platform/source; do not assume 20 V.	Verify 5 V default VBUS first, then observe negotiation and final contract.	PD communication / VBUS transition when negotiation succeeds.

Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 30 checked

Checked	#	Signal / Rail	Failure Isolation Hint	Technician Notes
Checked	1	Adapter / DC-IN main railSchematic p.3	No input: inspect adapter/port, fuse, protection MOSFETs and shorted PBUS/system rail. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	2	ACDETSchematic p.82	Incorrect ACDET: inspect divider, charger supply and adapter path before replacing the charger IC. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	3	ACOK / ACINSchematic p.5	Missing: validate charger VCC, ACDET, source qualification and pull-up rail. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	4	REGN / charger LDOSchematic p.84	Missing with valid input/VCC: investigate charger enable, supply and IC condition. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	5	3V always-on / S5 railSchematic p.3	Missing: inspect always-on controller enable/input, shorted load and power-good prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	6	5V always-on / S5 railSchematic p.3	Missing: inspect always-on controller, enable, shorted load and input supply. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	7	EC / SMC supplySchematic p.5	Missing/unstable EC supply prevents power-button and sequencing logic. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	8	32.768 kHz RTC / EC clockSchematic p.11	Absent clock: verify oscillator supply, crystal network and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	9	RSMRST#Schematic p.5	Held reset: work backward through always-on rails, RTC/clock, EC/SMC and PCH/SoC prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	10	PWRBTN# / power switchSchematic p.11	No transition: inspect button, connector, pull-up and EC/SMC input path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	11	SLP_S5#Schematic p.3	No transition: verify RSMRST#, firmware state, EC/SMC handshake and PCH/SoC prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	12	SLP_S4#Schematic p.3	If missing, work backward through S5 prerequisites and firmware/EC handoff. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	13	SLP_S3#Schematic p.3	If missing, check upstream sleep-state logic, EC/SMC and platform power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	14	Memory VDD / VDDQSchematic p.3	Missing/low: inspect memory VR enable, short/load and power-state prerequisite. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	15	VR_ON / CPU VR enableSchematic p.5	Missing: do not condemn VR controller; trace upstream sleep/power-good/EC logic. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	16	CPU VCORESchematic p.88	0 V with valid enable: inspect VR input, controller, phases, current limit and rail resistance. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	17	CPU VR power-good / VR_RDYSchematic p.5	Missing: investigate VR feedback/phase faults/overcurrent and rail stability. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	18	SVID clock/dataSchematic p.15	No activity with prerequisites valid: inspect CPU/VR bus path and controller supplies. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	19	SYS_PWROK / ALL_SYS_PWRGDSchematic p.5	Missing: identify the upstream rail or PGOOD that has not completed. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	20	PLTRST# / platform resetSchematic p.5	Held reset: verify firmware/SPI activity, clocks, SoC/PCH rails and PWROK chain. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	21	BIOS / SPI flash supplySchematic p.9	Wrong/missing supply: inspect flash power switch/rail and shorts before programming. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	22	SPI chip-selectSchematic p.6	No activity: sequence may not have reached firmware fetch; verify upstream reset/clock/power first. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	23	SPI clockSchematic p.6	CS activity without clock suggests bus/controller issue; no bus activity may be upstream sequencing. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	24	LCD / eDP panel powerSchematic p.6	Missing: inspect panel enable, fuse/load switch, shorted cable/panel and upstream display prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	25	eDP HPDSchematic p.6	Missing: inspect panel power, cable/connector and HPD path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	26	eDP AUXSchematic p.6	No AUX with power/HPD valid: inspect cable, panel and source path; do not infer GPU fault from one reading. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	27	Backlight PWMSchematic p.6	Missing PWM with enable present: inspect brightness control source and firmware/EC path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	28	Battery SMBusSchematic p.3	Stuck/no activity: inspect battery presence, pull-ups, bus shorts, EC/charger and pack. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	29	USB-C CC1 / CC2Schematic p.16	Abnormal state: inspect port, ESD/protection, pull networks and PD controller supply before IC replacement. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	30	PD negotiation / contractSchematic p.6	No contract: verify CC state, controller supply, dead-battery path, firmware and source/cable compatibility. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence

V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet

Adapter connectedANo successful-repair baseline yet

StandbyANo successful-repair baseline yet

Power-button pressANo successful-repair baseline yet

CPU initializationANo successful-repair baseline yet

BIOS activityANo successful-repair baseline yet

POSTANo successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for LA-K092P.

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 11
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD

LA-L161P

Revision: 0.1

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 11
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD