TCS Pune

GL503GE – Bench Power & Signal Checklist

Board-specific bench checklist derived from supplied schematic source(s) for GL503GE 1.0. Only signals confidently located in supplied source text were added; missing thresholds remain technician-verified rather than guessed.

V4.7 · REVISION SAFETY

GL503GE · Rev 1.0

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 GL503GEExpert⏱ 60-180 minutes📋 5 steps

Compatible models: ASUS GL503GE / GL703GE

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify board/revision before using reference values.

🛠 Required Tools

  • Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required
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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): GL503GE REV1.0 (1).pdf | GL503GE REV1.0 BoardView (1).pdf

Board profile

Power & Control Architecture

Platform / ODMASUS Coffee Lake-H / N17P
CPU / SoCIntel Kaby Lake
MemoryDDR4
EC / SIOIT8296
ChargerBQ24780SRUYR
BIOS / SPIW25Q128JVSSIQ
Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#StageSignal / RailFrom -> ToRefStateExpectedDMMOscilloscope
1DC InputAdapter / DC-IN main railInput connector / protection pathGL503GE schematic p.36Follow chronological sequenceBoard-specific adapter/input voltage; verify adapter or USB-C contract and schematic.Measure DC to ground at the input/protection path.Flat DC; investigate collapse or excessive ripple.
2ChargerACDETAdapter detect -> chargerGL503GE schematic p.36Follow chronological sequenceBoard/charger-IC specific adapter-detect level.Measure ACDET against charger datasheet/schematic.Stable qualification level after adapter insertion.
3ChargerACOK / ACINCharger -> EC/SMCGL503GE schematic p.3Follow chronological sequenceValid adapter-present logic state; polarity is board/IC specific.Measure logic level and insertion/removal transition.Clean state transition.
4Always-On3V always-on / S5 railAlways-on 3V railGL503GE schematic p.2Follow chronological sequenceNominal board-specific 3V-class always-on rail.Measure at regulator output coil/capacitor.Clean startup and stable DC.
5Always-On5V always-on / S5 railAlways-on 5V railGL503GE schematic p.11Follow chronological sequenceNominal board-specific 5V-class always-on rail.Measure at regulator output coil/capacitor.Clean startup and stable DC.
6EC / SMCEC / KBC / SMC supplyEC/KBC/SMC powerGL503GE schematic p.1Follow chronological sequenceController supply must be valid before sequence outputs are expected.Measure controller supply rail(s).Flat DC; no repeated collapse.
7EC / SMC32.768 kHz RTC / EC clockRTC / EC low-frequency clockGL503GE schematic p.12Follow chronological sequenceStable low-frequency oscillation where applicable.Use high-impedance scope probe; avoid loading crystal nodes.~32.768 kHz waveform where exposed.
8ResetRSMRST#EC/PCH reset sequenceGL503GE schematic p.11Follow chronological sequenceBoard-specific deasserted state after resume-well prerequisites.Measure logic state through power transition.Clean assertion/deassertion.
9Power ButtonPWRBTN#Button/EC -> PCH/SoCGL503GE schematic p.11Follow chronological sequenceValid board-specific button transition when pressed.Observe idle and pressed state.Clean pulse/transition.
10Sleep / SequenceSLP_S5#PCH/SoC -> power sequencingGL503GE schematic p.11Follow chronological sequenceBoard-specific deassertion when leaving S5.Measure during power-on sequence.Clean transition.
11Sleep / SequenceSLP_S4#PCH/SoC -> power sequencingGL503GE schematic p.11Follow chronological sequenceBoard-specific deassertion when leaving S4.Measure during power-on sequence.Clean transition.
12Sleep / SequenceSLP_S3#PCH/SoC -> main railsGL503GE schematic p.11Follow chronological sequenceBoard-specific deassertion when entering S0.Measure during power-on sequence.Clean transition.
13VR EnableVR_ON / VR enableEC/PCH -> VR controllerGL503GE schematic p.3Follow chronological sequenceBoard-specific VR enable state.Measure at VR controller enable pin/path.Clean assertion before core rail rise.
14CPU / SoC VRVCORE / CPU core railCPU/SoC core VR outputGL503GE schematic p.22Follow chronological sequenceDynamic low-voltage core rail; exact value depends on CPU state.Measure at core inductors with suitable meter/scope.Controlled ramp; switching activity under load.
15Power GoodSYS_PWROK / ALL_SYS_PWRGDSystem power-good chainGL503GE schematic p.11Follow chronological sequenceValid board-specific power-good after required rails are stable.Measure logic state after main rails rise.Clean assertion.
16ResetPLTRST#PCH/SoC -> platform devicesGL503GE schematic p.3Follow chronological sequenceDeasserted platform reset after clocks, rails and power-good prerequisites.Measure during startup.Clean reset release.
17BIOS / SPISPI chip selectController -> SPI flashGL503GE schematic p.5Follow chronological sequenceIdle/inactive with access pulses during firmware fetch.Scope during power-on/reset release.Chip-select pulse bursts.
18BIOS / SPISPI clockController -> SPI flashGL503GE schematic p.10Follow chronological sequenceClock bursts during flash access.Scope during firmware access.High-frequency clock bursts.
19DisplayLCD / eDP panel powerPanel power pathGL503GE schematic p.12Follow chronological sequenceBoard-specific panel logic supply from schematic.Measure at panel fuse/load switch/connector.Stable DC after panel enable.
20DisplayeDP HPDPanel -> GPU/PCH/SoCGL503GE schematic p.43Follow chronological sequenceValid board-specific HPD state when panel is detected.Measure with panel connected and powered.Clean logic level/transition.
21DisplayeDP AUXGPU/PCH/SoC panelGL503GE schematic p.4Follow chronological sequenceAUX transactions during panel detection/EDID/link setup.Use suitable scope/differential method; avoid loading the bus.Bidirectional AUX activity.
22DisplayBacklight enableEC/PCH/GPU -> backlightGL503GE schematic p.30Follow chronological sequenceBoard-specific active state after panel initialization.Measure enable logic when backlight should be active.Clean assertion.
23Battery / BusSMBus / I2C activityEC/charger/battery busGL503GE schematic p.1Follow chronological sequencePulled-high idle with transaction bursts when devices are queried.Scope clock/data and confirm pull-up rail.I2C/SMBus clock/data bursts.
24USB-C / PDUSB-C CC1 / CC2USB-C port -> PD controllerGL503GE schematic p.1Follow chronological sequenceValid attachment/orientation state; exact voltage depends on Rp/Rd and role.Measure CC states according to controller datasheet and port orientation.Observe attach/orientation changes.
25USB-C / PDPD negotiation / contractUSB-C PD controllerGL503GE schematic p.1Follow chronological sequenceContract may be 5/9/15/20 V or PPS depending platform/source.Verify default VBUS first, then observe negotiation and final contract.PD communication / VBUS transition when negotiation succeeds.
Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 25 checked
Checked#Signal / RailMeasuredObserved Waveform / LogicResultFailure Isolation HintTechnician Notes
1Adapter / DC-IN main railGL503GE schematic p.36No input: inspect source, connector, fuse/protection path and system-rail short.
Additional readings
Technician evidence
2ACDETGL503GE schematic p.36Abnormal ACDET: inspect divider, charger VCC, source and surrounding passives.
Additional readings
Technician evidence
3ACOK / ACINGL503GE schematic p.3Missing: verify charger VCC, ACDET, source qualification and pull-up rail.
Additional readings
Technician evidence
43V always-on / S5 railGL503GE schematic p.2Missing: inspect regulator input/enable, shorted load and prerequisite power-good.
Additional readings
Technician evidence
55V always-on / S5 railGL503GE schematic p.11Missing: inspect regulator input/enable, shorted load and prerequisite power-good.
Additional readings
Technician evidence
6EC / KBC / SMC supplyGL503GE schematic p.1Missing/unstable controller supply blocks power-button and sequencing logic.
Additional readings
Technician evidence
732.768 kHz RTC / EC clockGL503GE schematic p.12Absent clock: verify oscillator supply, crystal network and controller state.
Additional readings
Technician evidence
8RSMRST#GL503GE schematic p.11Missing: check RTC/resume-well rails, EC/SMC state and upstream power-good.
Additional readings
Technician evidence
9PWRBTN#GL503GE schematic p.11No transition: inspect button, EC path, pull-up and controller state.
Additional readings
Technician evidence
10SLP_S5#GL503GE schematic p.11Missing: diagnose upstream reset/firmware/power prerequisites.
Additional readings
Technician evidence
11SLP_S4#GL503GE schematic p.11Missing: inspect prior sleep/reset prerequisites.
Additional readings
Technician evidence
12SLP_S3#GL503GE schematic p.11Missing: inspect prior sleep/reset/firmware prerequisites.
Additional readings
Technician evidence
13VR_ON / VR enableGL503GE schematic p.3Missing: inspect sleep signals, EC/PCH outputs and interlocks.
Additional readings
Technician evidence
14VCORE / CPU core railGL503GE schematic p.22Missing: inspect VR enable, controller supply, phases and SVID/control prerequisites.
Additional readings
Technician evidence
15SYS_PWROK / ALL_SYS_PWRGDGL503GE schematic p.11Missing: find the first upstream rail or PGOOD that is absent.
Additional readings
Technician evidence
16PLTRST#GL503GE schematic p.3Missing: trace SYS_PWROK/VR_PWRGD/VR enable/sleep/reset prerequisites first.
Additional readings
Technician evidence
17SPI chip selectGL503GE schematic p.5No activity: verify sequence reached firmware fetch before suspecting the flash.
Additional readings
Technician evidence
18SPI clockGL503GE schematic p.10CS without clock suggests bus/controller path; no bus activity may be upstream sequence.
Additional readings
Technician evidence
19LCD / eDP panel powerGL503GE schematic p.12Missing: inspect panel enable, fuse/load switch, shorted cable/panel and display prerequisites.
Additional readings
Technician evidence
20eDP HPDGL503GE schematic p.43Missing: inspect panel power, cable/connector and HPD path.
Additional readings
Technician evidence
21eDP AUXGL503GE schematic p.4No AUX with power/HPD valid: inspect cable, panel and source path.
Additional readings
Technician evidence
22Backlight enableGL503GE schematic p.30Missing: inspect lid/Hall state, display initialization, firmware and control path.
Additional readings
Technician evidence
23SMBus / I2C activityGL503GE schematic p.1Stuck/no activity: inspect pull-ups, shorts and powered bus participants.
Additional readings
Technician evidence
24USB-C CC1 / CC2GL503GE schematic p.1Abnormal state: inspect connector, ESD/protection, pull networks and controller supply.
Additional readings
Technician evidence
25PD negotiation / contractGL503GE schematic p.1No contract: verify CC state, controller supply, dead-battery path, firmware and cable/source compatibility.
Additional readings
Technician evidence
V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for GL503GE.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.

V4.9 Diagnostic Timeline

Repair Timeline

Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.

    The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.

    GUIDED BIOS DIAGNOSTICS · V5.1

    BIOS / SPI Flash Diagnostic Record

    Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.

    Original BIOS dump

    The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.

    Repaired BIOS dump

    Stored as a separate attachment. Uploading it never modifies the original dump.

    Final diagnostic decision

    Is the problem solved?

    Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.

    V5.0 Repair Case Intelligence

    Board Repair Dashboard

    Aggregate repair patterns for GL503GE · Rev 1.0. Historical patterns are references, not proof of the current fault.

    0Recorded repairs
    0.0%Solved
    Not enough timeline dataAverage diagnosis time
    0Rework cases

    Common symptoms

    No structured data yet.

    Frequently failed rails / signals

    No structured data yet.

    Frequently replaced / repaired ICs

    No structured data yet.

    Common root causes

    No structured data yet.

    Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.

    USB-C / PD DIAGNOSTICS · V5.2

    USB-C Power Delivery Diagnostic Record

    Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.

    USB-C port fault checklist

    Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.

    DISPLAY / NO-DISPLAY DIAGNOSTICS · V5.3

    Internal & External Display Diagnostic Record

    Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.

    Internal vs external display decision tree

    Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.

    Record the internal and external display results to show decision guidance.
    💰

    Estimated repair cost at TCS Pune

    ₹4,000 – ₹15,000

    Final price confirmed after free device inspection. Includes 6-month warranty.

    Get exact quote ↗
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