Board-specific bench checklist derived from supplied schematic source(s) for FX705GD 2.0. Only signals confidently located in supplied source text were added; missing thresholds remain technician-verified rather than guessed.
V4.7 · REVISION SAFETY
FX705GD · Rev 2.0
Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.
Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.
🔌 FX705GDExpert⏱ 60-180 minutes📋 5 steps
Compatible models: ASUS FX705GD
⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify board/revision before using reference values.
🛠 Required Tools
Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required
0 / 5 done
Progress saved in browser.
Schematic-derived bench record
Bench Manual & Source Coverage
Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): FX705GD REV2.0.pdf
Board profile
Power & Control Architecture
Platform / ODMASUS Coffee Lake-H / N17P
CPU / SoCIntel Skylake
MemoryDDR4
EC / SIOIT8987E
ChargerBQ24780SRUYR
BIOS / SPIW25Q128JVSIQ
Table A
Chronological Power Sequence
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
#
Stage
Signal / Rail
From -> To
Ref
State
Expected
DMM
Oscilloscope
1
DC Input
Adapter / DC-IN main rail
Input connector / protection path
FX705GD schematic p.31
Follow chronological sequence
Board-specific adapter/input voltage; verify adapter or USB-C contract and schematic.
Measure DC to ground at the input/protection path.
Flat DC; investigate collapse or excessive ripple.
2
Charger
ACDET
Adapter detect -> charger
FX705GD schematic p.57
Follow chronological sequence
Board/charger-IC specific adapter-detect level.
Measure ACDET against charger datasheet/schematic.
Stable qualification level after adapter insertion.
3
Charger
ACOK / ACIN
Charger -> EC/SMC
FX705GD schematic p.5
Follow chronological sequence
Valid adapter-present logic state; polarity is board/IC specific.
Measure logic level and insertion/removal transition.
Clean state transition.
4
EC / SMC
EC / KBC / SMC supply
EC/KBC/SMC power
FX705GD schematic p.1
Follow chronological sequence
Controller supply must be valid before sequence outputs are expected.
Measure controller supply rail(s).
Flat DC; no repeated collapse.
5
EC / SMC
32.768 kHz RTC / EC clock
RTC / EC low-frequency clock
FX705GD schematic p.19
Follow chronological sequence
Stable low-frequency oscillation where applicable.
Use high-impedance scope probe; avoid loading crystal nodes.
~32.768 kHz waveform where exposed.
6
Reset
RSMRST#
EC/PCH reset sequence
FX705GD schematic p.18
Follow chronological sequence
Board-specific deasserted state after resume-well prerequisites.
Measure logic state through power transition.
Clean assertion/deassertion.
7
Power Button
PWRBTN#
Button/EC -> PCH/SoC
FX705GD schematic p.18
Follow chronological sequence
Valid board-specific button transition when pressed.
Observe idle and pressed state.
Clean pulse/transition.
8
Sleep / Sequence
SLP_S5#
PCH/SoC -> power sequencing
FX705GD schematic p.18
Follow chronological sequence
Board-specific deassertion when leaving S5.
Measure during power-on sequence.
Clean transition.
9
Sleep / Sequence
SLP_S4#
PCH/SoC -> power sequencing
FX705GD schematic p.18
Follow chronological sequence
Board-specific deassertion when leaving S4.
Measure during power-on sequence.
Clean transition.
10
Sleep / Sequence
SLP_S3#
PCH/SoC -> main rails
FX705GD schematic p.18
Follow chronological sequence
Board-specific deassertion when entering S0.
Measure during power-on sequence.
Clean transition.
11
Power Good
SUS_PWRGD
Suspend rails -> logic
FX705GD schematic p.23
Follow chronological sequence
Valid suspend-power-good state after required rails stabilize.
Measure after always-on/suspend rails.
Clean assertion.
12
VR Enable
VR_ON / VR enable
EC/PCH -> VR controller
FX705GD schematic p.42
Follow chronological sequence
Board-specific VR enable state.
Measure at VR controller enable pin/path.
Clean assertion before core rail rise.
13
CPU / SoC VR
VCORE / CPU core rail
CPU/SoC core VR output
FX705GD schematic p.9
Follow chronological sequence
Dynamic low-voltage core rail; exact value depends on CPU state.
Measure at core inductors with suitable meter/scope.
Controlled ramp; switching activity under load.
14
Power Good
SYS_PWROK / ALL_SYS_PWRGD
System power-good chain
FX705GD schematic p.7
Follow chronological sequence
Valid board-specific power-good after required rails are stable.
Measure logic state after main rails rise.
Clean assertion.
15
Reset
PLTRST#
PCH/SoC -> platform devices
FX705GD schematic p.7
Follow chronological sequence
Deasserted platform reset after clocks, rails and power-good prerequisites.
Measure during startup.
Clean reset release.
16
BIOS / SPI
SPI chip select
Controller -> SPI flash
FX705GD schematic p.4
Follow chronological sequence
Idle/inactive with access pulses during firmware fetch.
Scope during power-on/reset release.
Chip-select pulse bursts.
17
BIOS / SPI
SPI clock
Controller -> SPI flash
FX705GD schematic p.16
Follow chronological sequence
Clock bursts during flash access.
Scope during firmware access.
High-frequency clock bursts.
18
Display
LCD / eDP panel power
Panel power path
FX705GD schematic p.15
Follow chronological sequence
Board-specific panel logic supply from schematic.
Measure at panel fuse/load switch/connector.
Stable DC after panel enable.
19
Display
eDP HPD
Panel -> GPU/PCH/SoC
FX705GD schematic p.15
Follow chronological sequence
Valid board-specific HPD state when panel is detected.
Measure with panel connected and powered.
Clean logic level/transition.
20
Display
eDP AUX
GPU/PCH/SoC panel
FX705GD schematic p.3
Follow chronological sequence
AUX transactions during panel detection/EDID/link setup.
Use suitable scope/differential method; avoid loading the bus.
Bidirectional AUX activity.
21
Display
Backlight PWM
EC/PCH/GPU -> backlight
FX705GD schematic p.15
Follow chronological sequence
PWM activity when brightness is nonzero; exact duty/frequency is platform specific.
Scope PWM and record duty/frequency.
Stable PWM waveform.
22
Battery / Bus
SMBus / I2C activity
EC/charger/battery bus
FX705GD schematic p.2
Follow chronological sequence
Pulled-high idle with transaction bursts when devices are queried.
Scope clock/data and confirm pull-up rail.
I2C/SMBus clock/data bursts.
Table B
Bench Reading & Fault Isolation
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
0 / 22 checked
Checked
#
Signal / Rail
Measured
Observed Waveform / Logic
Result
Failure Isolation Hint
Technician Notes
1
Adapter / DC-IN main railFX705GD schematic p.31
No input: inspect source, connector, fuse/protection path and system-rail short.Additional readings
Missing: inspect panel power, cable/connector and HPD path.Additional readings
Technician evidence
20
eDP AUXFX705GD schematic p.3
No AUX with power/HPD valid: inspect cable, panel and source path.Additional readings
Technician evidence
21
Backlight PWMFX705GD schematic p.15
Missing PWM with enable present: inspect brightness-control source and firmware/EC path.Additional readings
Technician evidence
22
SMBus / I2C activityFX705GD schematic p.2
Stuck/no activity: inspect pull-ups, shorts and powered bus participants.Additional readings
Technician evidence
V4.0 · BOARD COMPONENT INTELLIGENCE
Component Index
Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.
Controller / IC
BIOS IC · W25Q128JVSIQ
Function
SPI firmware flash memory
Related rails / signalsNot identified from current checklist.
Enable / sequencingNot identified from current checklist.
PGOOD / statusNot identified from current checklist.
Input
Controller
Output
SPI flash
Checklist tests
SPI chip select u2014 Idle/inactive with access pulses during firmware fetch.
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Current sequence:No readings yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
V4.4 Board Knowledge
Previous Solved Cases
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
Live match: Mark a bench signal FAIL to check previous solved cases for FX705GD.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
V4.5 · SIMILAR BOARD / PLATFORM MATCHING
Reference Boards
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.
V4.9 Diagnostic Timeline
Repair Timeline
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
GUIDED BIOS DIAGNOSTICS · V5.1
BIOS / SPI Flash Diagnostic Record
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
Original BIOS dump
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Repaired BIOS dump
Stored as a separate attachment. Uploading it never modifies the original dump.
Final diagnostic decision
Is the problem solved?
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Repair QC & Final VerificationRequired before solved publication
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
V5.0 Repair Case Intelligence
Board Repair Dashboard
Aggregate repair patterns for FX705GD · Rev 2.0. Historical patterns are references, not proof of the current fault.
0Recorded repairs
0.0%Solved
Not enough timeline dataAverage diagnosis time
0Rework cases
Common symptoms
No structured data yet.
Frequently failed rails / signals
No structured data yet.
Frequently replaced / repaired ICs
No structured data yet.
Common root causes
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
USB-C / PD DIAGNOSTICS · V5.2
USB-C Power Delivery Diagnostic Record
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
USB-C port fault checklist
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
DISPLAY / NO-DISPLAY DIAGNOSTICS · V5.3
Internal & External Display Diagnostic Record
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Internal vs external display decision tree
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
Record the internal and external display results to show decision guidance.
💰
Estimated repair cost at TCS Pune
₹4,000 – ₹15,000
Final price confirmed after free device inspection. Includes 6-month warranty.
