TCS Pune

DAX63CMB6C0 – Bench Power & Signal Checklist

Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.

V4.7 · REVISION SAFETY

DAX63CMB6C0 · Rev 1A

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 DAX63CMB6C0Expert⏱ 60-180 minutes📋 5 steps

Compatible models: ProBook 450 G3 / 470 G3

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Use a short ground spring for high-speed oscilloscope probing.

🛠 Required Tools

  • Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required
0 / 5 done
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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): HP ProBook 450 G3 Quanta X63C DAX63CMB6C0 r1a 13102015.pdf

Board profile

Power & Control Architecture

Platform / ODMQuanta X63C
CPU / SoCIntel Skylake-U
MemoryDDR3L
EC / SIONPCE586H
ChargerBQ24780SRUYR
Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#StageSignal / RailFrom -> ToRefStateExpectedDMMOscilloscope
1DC InputAdapter / DC-IN main railInput connector / protection pathDAX63CMB6C0 schematic p.62Follow chronological sequenceBoard-specific adapter/input voltage; verify source and schematic.Measure DC to ground at the input/protection path.Flat DC; investigate collapse or excessive ripple.
2ChargerACDETCharger adapter-detect dividerDAX63CMB6C0 schematic p.49Follow chronological sequenceMust be within the charger IC valid adapter-detect window; verify exact charger datasheet.Measure DC at ACDET.Stable analog level after adapter insertion.
3ChargerACOK / ACINCharger -> ECDAX63CMB6C0 schematic p.49Follow chronological sequenceValid adapter-present logic state; polarity is board/IC specific.Measure logic level and insertion/removal transition.Clean state transition.
4Always-On3V always-on / S5 railAlways-on 3V railDAX63CMB6C0 schematic p.3Follow chronological sequenceNominal board-specific 3V-class always-on rail.Measure at regulator output coil/capacitor.Clean startup and stable DC.
5Always-On5V always-on / S5 railAlways-on 5V railDAX63CMB6C0 schematic p.17Follow chronological sequenceNominal board-specific 5V-class always-on rail.Measure at regulator output coil/capacitor.Clean startup and stable DC.
6EC / SMCEC / KBC / SMC supplyEC/KBC/SMC powerDAX63CMB6C0 schematic p.1Follow chronological sequenceController supply must be valid before sequence outputs are expected.Measure controller supply rail(s).Flat DC; no repeated collapse.
7EC / SMC32.768 kHz RTC / EC clockRTC / EC low-frequency clockDAX63CMB6C0 schematic p.1Follow chronological sequenceStable low-frequency oscillation where applicable.Use high-impedance scope probe; avoid loading crystal nodes.~32.768 kHz waveform where exposed.
8ResetRSMRST#EC/PCH reset sequenceDAX63CMB6C0 schematic p.3Follow chronological sequenceBoard-specific deasserted state after resume-well prerequisites.Measure logic state through power transition.Clean assertion/deassertion.
9Power ButtonPWRBTN#Button/EC -> PCH/SoCDAX63CMB6C0 schematic p.3Follow chronological sequenceValid board-specific button transition when pressed.Observe idle and pressed state.Clean pulse/transition.
10Sleep StateSLP_S5#PCH/SoC -> power sequenceDAX63CMB6C0 schematic p.3Follow chronological sequenceCorrect state transition for exit from S5.Measure during power-button event.Clean transition without repeated cycling.
11Sleep StateSLP_S4#PCH/SoC -> power sequenceDAX63CMB6C0 schematic p.3Follow chronological sequenceCorrect state transition for exit from S4.Measure during startup.Clean transition.
12Sleep StateSLP_S3#PCH/SoC -> power sequenceDAX63CMB6C0 schematic p.3Follow chronological sequenceCorrect state transition for exit from S3.Measure during startup.Clean transition.
13MemoryMemory rail / VDDQMemory powerDAX63CMB6C0 schematic p.13Follow chronological sequenceBoard/memory-generation specific memory supply.Measure at memory regulator output.Stable DC after enable.
14CPU VRVR_ON / CPU VR enableCPU VR enableDAX63CMB6C0 schematic p.48Follow chronological sequenceEnable must assert before CPU core rails rise.Measure enable logic through startup.Clean assertion.
15CPU VRCPU VCORECPU core regulator outputDAX63CMB6C0 schematic p.3Follow chronological sequenceDynamic CPU core voltage; exact value depends on CPU state.Measure at CPU VR output coil.Dynamic but stable under state/load changes.
16Power GoodVR / system PGOODRegulators -> EC/PCH/SoCDAX63CMB6C0 schematic p.3Follow chronological sequencePower-good signals should assert only after monitored rails are valid.Measure logic and sequence timing.Clean assertion after rail stabilization.
17ResetPLTRST#PCH/SoC platform resetDAX63CMB6C0 schematic p.3Follow chronological sequenceDeasserts after required rails, clocks and power-good conditions are valid.Measure during startup.Clean reset release after prerequisites.
18BIOS / SPISPI CS# / CLK / MOSI / MISOPCH/SoC BIOS flashDAX63CMB6C0 schematic p.3Follow chronological sequenceActivity expected during firmware fetch; exact voltage depends on flash type.Use scope on CLK/CS/data lines.Burst activity during boot.
19SMBus / I2CSMBus / I2C activityEC/charger/battery/system busesDAX63CMB6C0 schematic p.3Follow chronological sequencePulled-high bus with transaction activity where devices are queried.Use scope; confirm idle level and bursts.Digital clock/data bursts.
20DisplayeDP AUX / HPDSoC/GPU -> panelDAX63CMB6C0 schematic p.5Follow chronological sequenceBoard-specific eDP link-management activity after display power prerequisites.Use scope and schematic-approved test points.AUX bursts / HPD logic where applicable.
21USB-C / PDUSB-C CC / PD negotiationUSB-C port -> PD controllerDAX63CMB6C0 schematic p.5Follow chronological sequenceObserve board-specific CC state and PD negotiation; do not assume 20 V is always required.Measure CC/VBUS with suitable tools and known-good adapter/cable.CC communication / negotiated VBUS transition where supported.
Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 21 checked
Checked#Signal / RailMeasuredObserved Waveform / LogicResultFailure Isolation HintTechnician Notes
1Adapter / DC-IN main railDAX63CMB6C0 schematic p.62No input: inspect adapter, connector, fuse/protection MOSFETs and system-rail short.
Additional readings
Technician evidence
2ACDETDAX63CMB6C0 schematic p.49Incorrect ACDET: inspect divider, charger supply and adapter path.
Additional readings
Technician evidence
3ACOK / ACINDAX63CMB6C0 schematic p.49Missing: verify charger VCC, ACDET/source qualification and pull-up rail.
Additional readings
Technician evidence
43V always-on / S5 railDAX63CMB6C0 schematic p.3Missing: inspect regulator input/enable, shorted load and prerequisite power-good.
Additional readings
Technician evidence
55V always-on / S5 railDAX63CMB6C0 schematic p.17Missing: inspect regulator input/enable, shorted load and prerequisite power-good.
Additional readings
Technician evidence
6EC / KBC / SMC supplyDAX63CMB6C0 schematic p.1Missing/unstable controller supply blocks power-button and sequencing logic.
Additional readings
Technician evidence
732.768 kHz RTC / EC clockDAX63CMB6C0 schematic p.1Absent clock: verify oscillator supply, crystal network and controller state.
Additional readings
Technician evidence
8RSMRST#DAX63CMB6C0 schematic p.3Missing: check RTC/resume-well rails, EC state and upstream power-good.
Additional readings
Technician evidence
9PWRBTN#DAX63CMB6C0 schematic p.3No transition: inspect button, EC path, pull-up and controller state.
Additional readings
Technician evidence
10SLP_S5#DAX63CMB6C0 schematic p.3Missing transition: inspect prerequisites, EC/PCH state and reset/power-good.
Additional readings
Technician evidence
11SLP_S4#DAX63CMB6C0 schematic p.3Missing transition: trace upstream sleep/reset prerequisites.
Additional readings
Technician evidence
12SLP_S3#DAX63CMB6C0 schematic p.3Missing transition: trace upstream sleep/reset prerequisites.
Additional readings
Technician evidence
13Memory rail / VDDQDAX63CMB6C0 schematic p.13Missing: inspect memory regulator input, enable, short and PGOOD.
Additional readings
Technician evidence
14VR_ON / CPU VR enableDAX63CMB6C0 schematic p.48Missing: check SLP_S3#/S0 prerequisites and EC/PCH power-good chain.
Additional readings
Technician evidence
15CPU VCOREDAX63CMB6C0 schematic p.3Missing with valid enable: inspect VR input, controller, phases and load short.
Additional readings
Technician evidence
16VR / system PGOODDAX63CMB6C0 schematic p.3Missing: identify which regulator/rail has not reached valid condition.
Additional readings
Technician evidence
17PLTRST#DAX63CMB6C0 schematic p.3Missing: work upstream through SYS_PWROK/VR PGOOD/sleep/reset chain.
Additional readings
Technician evidence
18SPI CS# / CLK / MOSI / MISODAX63CMB6C0 schematic p.3No activity: verify flash supply/reset, PCH prerequisites, EC state and firmware path.
Additional readings
Technician evidence
19SMBus / I2C activityDAX63CMB6C0 schematic p.3Stuck bus: isolate pull-ups and devices; no activity may be a prerequisite/state issue.
Additional readings
Technician evidence
20eDP AUX / HPDDAX63CMB6C0 schematic p.5No activity: verify panel VCC, cable/connector, HPD, GPU/SoC state and firmware.
Additional readings
Technician evidence
21USB-C CC / PD negotiationDAX63CMB6C0 schematic p.5No negotiation: check port, CC path, PD-controller supply, dead-battery path and charger handoff.
Additional readings
Technician evidence
V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for DAX63CMB6C0.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

REFERENCE BOARD

FX705GD

Revision: 2.0

2/5 shared matching attributes
  • Same charger ICBQ24780SRUYR
  • Same CPU generation / model seriesINTEL CORE GEN 6
Open reference checklist →

Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.

V4.9 Diagnostic Timeline

Repair Timeline

Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.

    The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.

    GUIDED BIOS DIAGNOSTICS · V5.1

    BIOS / SPI Flash Diagnostic Record

    Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.

    Original BIOS dump

    The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.

    Repaired BIOS dump

    Stored as a separate attachment. Uploading it never modifies the original dump.

    Final diagnostic decision

    Is the problem solved?

    Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.

    V5.0 Repair Case Intelligence

    Board Repair Dashboard

    Aggregate repair patterns for DAX63CMB6C0 · Rev 1A. Historical patterns are references, not proof of the current fault.

    0Recorded repairs
    0.0%Solved
    Not enough timeline dataAverage diagnosis time
    0Rework cases

    Common symptoms

    No structured data yet.

    Frequently failed rails / signals

    No structured data yet.

    Frequently replaced / repaired ICs

    No structured data yet.

    Common root causes

    No structured data yet.

    Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.

    USB-C / PD DIAGNOSTICS · V5.2

    USB-C Power Delivery Diagnostic Record

    Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.

    USB-C port fault checklist

    Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.

    DISPLAY / NO-DISPLAY DIAGNOSTICS · V5.3

    Internal & External Display Diagnostic Record

    Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.

    Internal vs external display decision tree

    Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.

    Record the internal and external display results to show decision guidance.
    💰

    Estimated repair cost at TCS Pune

    ₹4,000 – ₹15,000

    Final price confirmed after free device inspection. Includes 6-month warranty.

    Get exact quote ↗
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