TCS Pune

NM-D521 – Bench Power & Signal Checklist

Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.

V4.7 · REVISION SAFETY

NM-D521 · Rev 1.0

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 NM-D521Expert⏱ 60-180 minutes📋 5 steps

Compatible models: Lenovo Ideapad 3-15ALC6 HS461 HS561A HS761 SCH

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Use a short ground spring for high-speed oscilloscope probing.

🛠 Required Tools

  • Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required
0 / 5 done
Progress saved in browser.
Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): Lenovo Ideapad 3-15ALC6 LCFC HS461_HS561A_HS761 NM-D521 Rev 1.0 SCH.pdf

Board profile

Power & Control Architecture

Platform / ODMLCFC
CPU / SoCAMD Renoir
MemoryLPDDR4
EC / SIOIT8227VG-128-CX
ChargerBQ24780SRUYR
Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#StageSignal / RailFrom -> ToRefStateExpectedDMMOscilloscope
1DC InputAdapter / DC-IN main railAdapter/battery input pathSchematic p.40Follow chronological sequence19-20 V typical for barrel adapters; USB-C depends on PD contractMeasure to ground at input connector/fuseFlat DC; inspect ripple only if unstable
2DC InputInput fuse - both sidesDC jack -> protection pathSchematic p.34Follow chronological sequenceSame voltage on both sides of input fuseDMM DC at both fuse sides to ground; continuity with power removedFlat DC
3ChargerACDET / adapter detectAdapter divider -> charger ICSchematic p.42Follow chronological sequenceIC-specific adapter-detect threshold; commonly about 2-3 VDMM DC at ACDETFlat DC
4ChargerACOK / AC_PRESENTCharger -> EC/PCHSchematic p.34Follow chronological sequenceValid logic state when adapter accepted; commonly logic highDMM logic levelClean logic transition when adapter is inserted
5ChargerACDRV / input MOSFET gate driveCharger -> input MOSFET gatesSchematic p.42Follow chronological sequenceGate drive above source when input path is enabled; exact value IC-specificMeasure gate and source; compare VGSGate should rise cleanly after valid adapter detect
6BatteryBattery positive / system battery railBattery connector -> charger/systemSchematic p.40Follow chronological sequencePack voltage appropriate to cell count and state of chargeDMM DC at battery positive to pack groundFlat DC; no excessive ripple
7RTCRTC / CMOS supplyRTC source -> PCH/SoCSchematic p.40Follow chronological sequenceTypically near 3 V; board-specificDMM DCFlat DC
8Always-On3 V always-on railStandby regulator -> EC/PCH/logicSchematic p.3Follow chronological sequence3.3 V nominal where this rail existsDMM DC at inductor/output capFlat DC with low ripple
9Always-On5 V always-on railStandby regulator -> peripheralsSchematic p.3Follow chronological sequence5.0 V nominal where design provides always-on 5 VDMM DC at inductor/output capFlat DC with low ripple
10Always-On1.8 V auxiliary railStandby regulator -> BIOS/PCH/logicSchematic p.3Follow chronological sequence1.8 V nominal where usedDMM DCFlat DC
11EC / SIO32.768 kHz RTC / EC clockCrystal/oscillator -> EC/PCHSchematic p.8Follow chronological sequenceStable 32.768 kHz where external low-frequency clock is usedDMM not reliable; use scopeStable low-amplitude sine/square waveform near 32.768 kHz
12MemoryDDR VDD / VDDQMemory regulator -> DIMM/SoCSchematic p.3Follow chronological sequenceDDR generation-specific rail; verify schematic and memory generationDMM DC at memory inductorFlat DC; low ripple
13MemoryDDR VPPMemory regulator -> DIMMSchematic p.4Follow chronological sequenceTypically 2.5 V for DDR4; generation-specificDMM DCFlat DC
14CPU / SoCVR_ON / CPU VR enableEC/PCH -> CPU VR controllerSchematic p.3Follow chronological sequenceActive before CPU core rail starts; logic level is board-specificDMM logic levelClean enable edge
15CPU / SoCVR power-goodCPU VR -> EC/PCHSchematic p.3Follow chronological sequenceAsserted after CPU VR outputs are validDMM logic levelClean assertion after core rail rises
16Power GoodSYS_PWROK / ALL_SYS_PWRGDPGOOD logic -> PCH/SoCSchematic p.9Follow chronological sequenceAsserted only after required S0 rails are validDMM logic levelClean delayed assertion
17BIOS / SPISPI_CS#PCH/SoC/EC -> SPI flashSchematic p.17Follow chronological sequenceIdle high with access pulses during firmware readsDMM not diagnostic; use scopeChip-select pulse bursts during start-up
18BIOS / SPISPI_CLKPCH/SoC/EC -> SPI flashSchematic p.8Follow chronological sequenceClock bursts during firmware accessDMM not diagnostic; use scopeHigh-frequency clock bursts
19DisplayeDP HPDPanel -> GPU/PCH/SoCSchematic p.5Follow chronological sequenceValid HPD logic state when panel is connected and poweredDMM logic levelClean logic level/transition
20DisplayBacklight enableEC/PCH/GPU -> panel/backlightSchematic p.34Follow chronological sequenceActive logic level when backlight should turn onDMM logic levelClean assertion after panel power
Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 20 checked
Checked#Signal / RailMeasuredObserved Waveform / LogicResultFailure Isolation HintTechnician Notes
1Adapter / DC-IN main railSchematic p.40No rail: inspect adapter, jack, fuse, protection MOSFETs
Additional readings
Technician evidence
2Input fuse - both sidesSchematic p.34Drop/open: replace only after checking downstream short
Additional readings
Technician evidence
3ACDET / adapter detectSchematic p.42Wrong level: verify divider, charger VCC and exact datasheet threshold
Additional readings
Technician evidence
4ACOK / AC_PRESENTSchematic p.34Missing: validate ACDET, charger supply, pull-up and charger IC
Additional readings
Technician evidence
5ACDRV / input MOSFET gate driveSchematic p.42No drive: check ACDET/ACOK, CMSRC and charger protection state
Additional readings
Technician evidence
6Battery positive / system battery railSchematic p.40Abnormal: verify pack, connector, BATFET and charger path
Additional readings
Technician evidence
7RTC / CMOS supplySchematic p.40Missing RTC can block RSMRST# and standby sequencing
Additional readings
Technician evidence
83 V always-on railSchematic p.3Missing/shorted: inspect standby controller enable and rail resistance
Additional readings
Technician evidence
95 V always-on railSchematic p.3Missing: inspect enable, controller supply, MOSFETs and load short
Additional readings
Technician evidence
101.8 V auxiliary railSchematic p.3Missing may block flash/PCH/EC logic on newer platforms
Additional readings
Technician evidence
1132.768 kHz RTC / EC clockSchematic p.8No clock: inspect crystal, load capacitors, supply and oscillator pins
Additional readings
Technician evidence
12DDR VDD / VDDQSchematic p.3Missing: check enable from S4/S3 logic and resistance to ground
Additional readings
Technician evidence
13DDR VPPSchematic p.4Missing may prevent memory training; check VPP regulator/switch
Additional readings
Technician evidence
14VR_ON / CPU VR enableSchematic p.3Missing: EC/PCH has stopped sequence; inspect previous power-good signals
Additional readings
Technician evidence
15VR power-goodSchematic p.3Missing: inspect VR feedback, phase faults, overcurrent/thermal protection
Additional readings
Technician evidence
16SYS_PWROK / ALL_SYS_PWRGDSchematic p.9Missing: identify which upstream PGOOD/rail is absent
Additional readings
Technician evidence
17SPI_CS#Schematic p.17No activity: sequence, reset, clock or controller may not have reached firmware fetch
Additional readings
Technician evidence
18SPI_CLKSchematic p.8CS toggles but no clock: inspect controller/bus; no bus activity: trace sequence first
Additional readings
Technician evidence
19eDP HPDSchematic p.5Missing: panel/cable/connector power or HPD trace issue
Additional readings
Technician evidence
20Backlight enableSchematic p.34Missing: lid/Hall state, graphics sequence, panel detection or firmware
Additional readings
Technician evidence
V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for NM-D521.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.

V4.9 Diagnostic Timeline

Repair Timeline

Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.

    The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.

    GUIDED BIOS DIAGNOSTICS · V5.1

    BIOS / SPI Flash Diagnostic Record

    Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.

    Original BIOS dump

    The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.

    Repaired BIOS dump

    Stored as a separate attachment. Uploading it never modifies the original dump.

    Final diagnostic decision

    Is the problem solved?

    Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.

    V5.0 Repair Case Intelligence

    Board Repair Dashboard

    Aggregate repair patterns for NM-D521 · Rev 1.0. Historical patterns are references, not proof of the current fault.

    0Recorded repairs
    0.0%Solved
    Not enough timeline dataAverage diagnosis time
    0Rework cases

    Common symptoms

    No structured data yet.

    Frequently failed rails / signals

    No structured data yet.

    Frequently replaced / repaired ICs

    No structured data yet.

    Common root causes

    No structured data yet.

    Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.

    USB-C / PD DIAGNOSTICS · V5.2

    USB-C Power Delivery Diagnostic Record

    Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.

    USB-C port fault checklist

    Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.

    DISPLAY / NO-DISPLAY DIAGNOSTICS · V5.3

    Internal & External Display Diagnostic Record

    Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.

    Internal vs external display decision tree

    Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.

    Record the internal and external display results to show decision guidance.
    💰

    Estimated repair cost at TCS Pune

    ₹4,000 – ₹15,000

    Final price confirmed after free device inspection. Includes 6-month warranty.

    Get exact quote ↗
    Ready when you are

    Need help with your laptop or computer?

    Send us the model and fault details. Start your repair request online or contact TCS Pune directly.

    ☎