Board-specific bench checklist derived from 2 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.
Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.
Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.
Compatible models: GE4B0 GE5B0
Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): GE4B0 GE5B0 NM-D011 REV 0.1 PDF .pdf | NM-D011 REV0.1.pdf
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
| # | Stage | Signal / Rail | From -> To | Ref | State | Expected | DMM | Oscilloscope |
|---|---|---|---|---|---|---|---|---|
| 1 | DC Input | Adapter / DC-IN main rail | Adapter/battery input path | Schematic p.6 | Follow chronological sequence | 19-20 V typical for barrel adapters; USB-C depends on PD contract | Measure to ground at input connector/fuse | Flat DC; inspect ripple only if unstable |
| 2 | DC Input | Input fuse - both sides | DC jack -> protection path | Schematic p.54 | Follow chronological sequence | Same voltage on both sides of input fuse | DMM DC at both fuse sides to ground; continuity with power removed | Flat DC |
| 3 | Charger | ACOK / AC_PRESENT | Charger -> EC/PCH | Schematic p.13 | Follow chronological sequence | Valid logic state when adapter accepted; commonly logic high | DMM logic level | Clean logic transition when adapter is inserted |
| 4 | Charger | REGN / charger internal LDO | Charger IC internal LDO | Schematic p.66 | Follow chronological sequence | IC-specific; often about 6 V on TI BQ families | DMM DC at REGN pin/cap | Flat DC |
| 5 | Battery | Battery positive / system battery rail | Battery connector -> charger/system | Schematic p.65 | Follow chronological sequence | Pack voltage appropriate to cell count and state of charge | DMM DC at battery positive to pack ground | Flat DC; no excessive ripple |
| 6 | Battery | Battery SMBus clock | EC/charger battery | Schematic p.7 | Follow chronological sequence | Pulled high with communication activity when battery is queried | DMM shows logic-high average; scope preferred | Digital clock bursts |
| 7 | Battery | Battery SMBus data | EC/charger battery | Schematic p.7 | Follow chronological sequence | Pulled high with bidirectional data activity | DMM shows logic-high average; scope preferred | Bidirectional data bursts |
| 8 | RTC | RTC / CMOS supply | RTC source -> PCH/SoC | Schematic p.13 | Follow chronological sequence | Typically near 3 V; board-specific | DMM DC | Flat DC |
| 9 | Always-On | 3 V always-on rail | Standby regulator -> EC/PCH/logic | Schematic p.3 | Follow chronological sequence | 3.3 V nominal where this rail exists | DMM DC at inductor/output cap | Flat DC with low ripple |
| 10 | Always-On | 5 V always-on rail | Standby regulator -> peripherals | Schematic p.18 | Follow chronological sequence | 5.0 V nominal where design provides always-on 5 V | DMM DC at inductor/output cap | Flat DC with low ripple |
| 11 | Always-On | 1.8 V auxiliary rail | Standby regulator -> BIOS/PCH/logic | Schematic p.3 | Follow chronological sequence | 1.8 V nominal where used | DMM DC | Flat DC |
| 12 | EC / SIO | EC / SIO supply | Standby rail -> EC/SIO | Schematic p.13 | Follow chronological sequence | Usually 3.3 V or design-specific auxiliary rail | DMM DC at EC decoupling capacitor | Flat DC |
| 13 | EC / SIO | 32.768 kHz RTC / EC clock | Crystal/oscillator -> EC/PCH | Schematic p.12 | Follow chronological sequence | Stable 32.768 kHz where external low-frequency clock is used | DMM not reliable; use scope | Stable low-amplitude sine/square waveform near 32.768 kHz |
| 14 | Power State | RSMRST# | EC/PCH resume-well logic | Schematic p.3 | Follow chronological sequence | Inactive/high after resume-well prerequisites are satisfied | DMM logic level | Clean low-to-high transition during standby initialization |
| 15 | Power Button | PWRBTN# / ON-OFF# input | Power button -> EC | Schematic p.13 | Follow chronological sequence | Normally high; clean active-low pulse on press | DMM min/max or scope | Single clean low pulse then returns high |
| 16 | Power Button | PBTN_OUT# / forwarded power button | EC -> PCH/SoC | Schematic p.13 | Follow chronological sequence | Forwarded active-low pulse after EC accepts button request | DMM min/max or scope | Clean active-low pulse |
| 17 | Power Sequence | SLP_S5# | PCH/SoC -> EC/power logic | Schematic p.13 | Follow chronological sequence | Deasserts/high when leaving S5; exact polarity/name platform-specific | DMM logic level | Step transition during power-on |
| 18 | Power Sequence | SLP_S4# | PCH/SoC -> EC/power logic | Schematic p.13 | Follow chronological sequence | Deasserts/high when leaving S4 | DMM logic level | Step transition |
| 19 | Power Sequence | SLP_S3# | PCH/SoC -> EC/power logic | Schematic p.13 | Follow chronological sequence | Deasserts/high when entering S0 | DMM logic level | Step transition |
| 20 | Memory | DDR VDD / VDDQ | Memory regulator -> DIMM/SoC | Schematic p.29 | Follow chronological sequence | DDR generation-specific rail; verify schematic and memory generation | DMM DC at memory inductor | Flat DC; low ripple |
| 21 | Memory | DDR VPP | Memory regulator -> DIMM | Schematic p.21 | Follow chronological sequence | Typically 2.5 V for DDR4; generation-specific | DMM DC | Flat DC |
| 22 | Memory | DRAM reset | CPU/PCH/SoC -> memory | Schematic p.4 | Follow chronological sequence | Released after memory power/clock prerequisites | DMM logic level | Clean reset release |
| 23 | CPU / SoC | VCCIO / CPU I/O rail | VR -> CPU/SoC | Schematic p.13 | Follow chronological sequence | Platform-specific, commonly around 0.8-1.05 V on Intel generations | DMM DC at inductor | Flat DC; switching only at PWM nodes |
| 24 | CPU / SoC | VR_ON / CPU VR enable | EC/PCH -> CPU VR controller | Schematic p.54 | Follow chronological sequence | Active before CPU core rail starts; logic level is board-specific | DMM logic level | Clean enable edge |
| 25 | CPU / SoC | CPU core rail | CPU VR -> processor core | Schematic p.54 | Follow chronological sequence | VID-controlled dynamic voltage; do not use a single universal value | DMM DC at core inductor | Multiphase switching on switch nodes; DC on output |
| 26 | CPU / SoC | VR power-good | CPU VR -> EC/PCH | Schematic p.54 | Follow chronological sequence | Asserted after CPU VR outputs are valid | DMM logic level | Clean assertion after core rail rises |
| 27 | CPU / SoC | SVID clock/data | CPU/SoC VR controller | Schematic p.14 | Follow chronological sequence | High-speed digital activity when CPU negotiates VID; logic level platform-specific | DMM not diagnostic; use scope | Digital bursts during CPU VR initialization |
| 28 | Power Good | SYS_PWROK / ALL_SYS_PWRGD | PGOOD logic -> PCH/SoC | Schematic p.13 | Follow chronological sequence | Asserted only after required S0 rails are valid | DMM logic level | Clean delayed assertion |
| 29 | Power Good | PCH_PWROK / SoC power-good | EC/PGOOD logic -> PCH/SoC | Schematic p.8 | Follow chronological sequence | Asserted when platform power prerequisites are valid | DMM logic level | Clean delayed assertion |
| 30 | Reset | PLTRST# | PCH/SoC -> platform devices | Schematic p.13 | Follow chronological sequence | Released/inactive after clocks and power-good conditions are satisfied | DMM logic level | Clean low-to-high release |
| 31 | BIOS / SPI | BIOS / SPI supply | Standby/main rail -> SPI flash | Schematic p.19 | Follow chronological sequence | Usually 3.3 V or 1.8 V depending flash device | DMM DC at flash VCC | Flat DC |
| 32 | BIOS / SPI | SPI_CS# | PCH/SoC/EC -> SPI flash | Schematic p.3 | Follow chronological sequence | Idle high with access pulses during firmware reads | DMM not diagnostic; use scope | Chip-select pulse bursts during start-up |
| 33 | BIOS / SPI | SPI_CLK | PCH/SoC/EC -> SPI flash | Schematic p.3 | Follow chronological sequence | Clock bursts during firmware access | DMM not diagnostic; use scope | High-frequency clock bursts |
| 34 | Display | eDP / LCD panel power | Load switch -> panel connector | Schematic p.3 | Follow chronological sequence | Usually 3.3 V or platform-specific panel logic rail | DMM DC at panel connector/fuse | Flat DC |
| 35 | Display | eDP HPD | Panel -> GPU/PCH/SoC | Schematic p.3 | Follow chronological sequence | Valid HPD logic state when panel is connected and powered | DMM logic level | Clean logic level/transition |
| 36 | Display | Backlight PWM | EC/PCH/GPU -> backlight driver | Schematic p.54 | Follow chronological sequence | PWM duty cycle controls brightness; amplitude board-specific | DMM may show averaged voltage; scope preferred | PWM waveform with variable duty cycle |
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
| Checked | # | Signal / Rail | Measured | Observed Waveform / Logic | Result | Failure Isolation Hint | Technician Notes |
|---|---|---|---|---|---|---|---|
| 1 | Adapter / DC-IN main railSchematic p.6 | No rail: inspect adapter, jack, fuse, protection MOSFETsAdditional readings | Technician evidence | ||||
| 2 | Input fuse - both sidesSchematic p.54 | Drop/open: replace only after checking downstream shortAdditional readings | Technician evidence | ||||
| 3 | ACOK / AC_PRESENTSchematic p.13 | Missing: validate ACDET, charger supply, pull-up and charger ICAdditional readings | Technician evidence | ||||
| 4 | REGN / charger internal LDOSchematic p.66 | Missing REGN with valid VCC may indicate charger IC faultAdditional readings | Technician evidence | ||||
| 5 | Battery positive / system battery railSchematic p.65 | Abnormal: verify pack, connector, BATFET and charger pathAdditional readings | Technician evidence | ||||
| 6 | Battery SMBus clockSchematic p.7 | No activity: check pull-up rail, EC/charger, battery presence and bus shortsAdditional readings | Technician evidence | ||||
| 7 | Battery SMBus dataSchematic p.7 | Stuck low/high: isolate battery/device and pull-up pathAdditional readings | Technician evidence | ||||
| 8 | RTC / CMOS supplySchematic p.13 | Missing RTC can block RSMRST# and standby sequencingAdditional readings | Technician evidence | ||||
| 9 | 3 V always-on railSchematic p.3 | Missing/shorted: inspect standby controller enable and rail resistanceAdditional readings | Technician evidence | ||||
| 10 | 5 V always-on railSchematic p.18 | Missing: inspect enable, controller supply, MOSFETs and load shortAdditional readings | Technician evidence | ||||
| 11 | 1.8 V auxiliary railSchematic p.3 | Missing may block flash/PCH/EC logic on newer platformsAdditional readings | Technician evidence | ||||
| 12 | EC / SIO supplySchematic p.13 | Must be stable before reset release and power-button processingAdditional readings | Technician evidence | ||||
| 13 | 32.768 kHz RTC / EC clockSchematic p.12 | No clock: inspect crystal, load capacitors, supply and oscillator pinsAdditional readings | Technician evidence | ||||
| 14 | RSMRST#Schematic p.3 | Held low: trace RTC/standby rails, EC firmware, PCH/SoC prerequisitesAdditional readings | Technician evidence | ||||
| 15 | PWRBTN# / ON-OFF# inputSchematic p.13 | No pulse: button board, cable, ESD/filter path, pull-up or EC pinAdditional readings | Technician evidence | ||||
| 16 | PBTN_OUT# / forwarded power buttonSchematic p.13 | Input pulse present but no output: EC firmware/state/prerequisite issueAdditional readings | Technician evidence | ||||
| 17 | SLP_S5#Schematic p.13 | Missing: PCH/SoC not exiting soft-off; verify RSMRST#, clocks, firmwareAdditional readings | Technician evidence | ||||
| 18 | SLP_S4#Schematic p.13 | Missing: memory/suspend rails may not enable; trace earlier state signalsAdditional readings | Technician evidence | ||||
| 19 | SLP_S3#Schematic p.13 | Missing: system remains in sleep state; verify firmware/PCH prerequisitesAdditional readings | Technician evidence | ||||
| 20 | DDR VDD / VDDQSchematic p.29 | Missing: check enable from S4/S3 logic and resistance to groundAdditional readings | Technician evidence | ||||
| 21 | DDR VPPSchematic p.21 | Missing may prevent memory training; check VPP regulator/switchAdditional readings | Technician evidence | ||||
| 22 | DRAM resetSchematic p.4 | Held reset: trace memory rails, clocks, SYS_PWROK and platform reset sequenceAdditional readings | Technician evidence | ||||
| 23 | VCCIO / CPU I/O railSchematic p.13 | Missing: check enable, short and regulator controllerAdditional readings | Technician evidence | ||||
| 24 | VR_ON / CPU VR enableSchematic p.54 | Missing: EC/PCH has stopped sequence; inspect previous power-good signalsAdditional readings | Technician evidence | ||||
| 25 | CPU core railSchematic p.54 | 0 V: verify VR_ON, controller supply, phase short and CPU conditionAdditional readings | Technician evidence | ||||
| 26 | VR power-goodSchematic p.54 | Missing: inspect VR feedback, phase faults, overcurrent/thermal protectionAdditional readings | Technician evidence | ||||
| 27 | SVID clock/dataSchematic p.14 | No activity with prerequisites valid: inspect CPU, VR controller, bus resistorsAdditional readings | Technician evidence | ||||
| 28 | SYS_PWROK / ALL_SYS_PWRGDSchematic p.13 | Missing: identify which upstream PGOOD/rail is absentAdditional readings | Technician evidence | ||||
| 29 | PCH_PWROK / SoC power-goodSchematic p.8 | Missing: trace aggregate power-good logic and required railsAdditional readings | Technician evidence | ||||
| 30 | PLTRST#Schematic p.13 | Held reset: check BIOS/SPI activity, clocks, PCH/SoC rails and PWROKAdditional readings | Technician evidence | ||||
| 31 | BIOS / SPI supplySchematic p.19 | Confirm flash marking before programming or applying external voltageAdditional readings | Technician evidence | ||||
| 32 | SPI_CS#Schematic p.3 | No activity: sequence, reset, clock or controller may not have reached firmware fetchAdditional readings | Technician evidence | ||||
| 33 | SPI_CLKSchematic p.3 | CS toggles but no clock: inspect controller/bus; no bus activity: trace sequence firstAdditional readings | Technician evidence | ||||
| 34 | eDP / LCD panel powerSchematic p.3 | Missing: check panel power enable, fuse/load switch and shorted panel/cableAdditional readings | Technician evidence | ||||
| 35 | eDP HPDSchematic p.3 | Missing: panel/cable/connector power or HPD trace issueAdditional readings | Technician evidence | ||||
| 36 | Backlight PWMSchematic p.54 | Enable present but no PWM: brightness/graphics/EC control path issueAdditional readings | Technician evidence |
Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.
Embedded controller / system I/O sequencing
No matching components found.
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Revision: 1.0
Revision: 0.1
Revision: 1.0
Revision: 0.2
Revision: 0.1
Revision: 0.1
Revision: 0.1
Revision: 0.1
Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Stored as a separate attachment. Uploading it never modifies the original dump.
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
Aggregate repair patterns for NM-D011 · Rev 0.1. Historical patterns are references, not proof of the current fault.
No structured data yet.
No structured data yet.
No structured data yet.
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
₹4,000 – ₹15,000
Final price confirmed after free device inspection. Includes 6-month warranty.
