TCS Pune

LA-J551P – Bench Power & Signal Checklist

Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.

V4.7 · REVISION SAFETY

LA-J551P, LA-H105P · Rev 02

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

I verified the physical board revision is Rev 02.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 LA-J551P, LA-H105PExpert⏱ 60-180 minutes📋 5 steps

Compatible models: Lenovo Xiaoxin AIR-14IIL 2020 FLMS0

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Use a short ground spring for high-speed oscilloscope probing.

🛠 Required Tools

Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required

0 / 5 done

1Confirm board identity and fault conditionRecord exact board code/revision, reported symptom, adapter/battery condition, and whether the board is in G3/S5/S0 or cycling.⚠ Use the exact board revision; similar board codes can use different power ICs.
2Unpowered resistance / short checkWith all power removed, check main input, always-on rails, memory rails and CPU/GPU rails for abnormal resistance to ground. Compare with known-good behavior when available.⚠ Low resistance on CPU/GPU core rails can be normal. Do not inject voltage until the rail topology and safe limit are confirmed.
3Trace the chronological power sequenceUse Table A in order. Stop at the first missing prerequisite, then diagnose upstream rather than replacing downstream components.⚠ A missing downstream signal is often a consequence, not the root cause.
4Capture dynamic signals with oscilloscopeUse a x10 probe and short ground connection. Capture power-button, sleep-state, reset, SPI, PWM and bus activity under the actual failure condition.⚠ Avoid long probe ground leads on switching nodes and high-speed buses.
5Record repair and verify all functionsAfter repair, repeat the failed stage, complete the sequence, test charging, battery, display, ports, thermal behavior, sleep/wake and multiple cold boots.⚠ Do not mark solved until the original symptom is reproducibly cleared.

Progress saved in browser.

Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): Lenovo Xiaoxin AIR-14IIL 2020 FLMS0 LA-J551P R02.pdf

Board profile

Power & Control Architecture

Platform / ODMCOMPAL

CPU / SoCIce Lake

PCH / ChipsetIce Lake

MemoryDDR5

EC / SIOKB9052

ChargerISL88739A

GPUNVIDIA

Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#	Stage	Signal / Rail	From -> To	Ref	State	Expected	DMM	Oscilloscope
1	DC Input	Adapter / DC-IN main rail	Adapter/battery input path	Schematic p.1	Follow chronological sequence	19-20 V typical for barrel adapters; USB-C depends on PD contract	Measure to ground at input connector/fuse	Flat DC; inspect ripple only if unstable
2	Charger	ACOK / AC_PRESENT	Charger -> EC/PCH	Schematic p.5	Follow chronological sequence	Valid logic state when adapter accepted; commonly logic high	DMM logic level	Clean logic transition when adapter is inserted
3	Charger	REGN / charger internal LDO	Charger IC internal LDO	Schematic p.52	Follow chronological sequence	IC-specific; often about 6 V on TI BQ families	DMM DC at REGN pin/cap	Flat DC
4	Battery	Battery positive / system battery rail	Battery connector -> charger/system	Schematic p.51	Follow chronological sequence	Pack voltage appropriate to cell count and state of charge	DMM DC at battery positive to pack ground	Flat DC; no excessive ripple
5	Battery	Battery SMBus clock	EC/charger battery	Schematic p.3	Follow chronological sequence	Pulled high with communication activity when battery is queried	DMM shows logic-high average; scope preferred	Digital clock bursts
6	Battery	Battery SMBus data	EC/charger battery	Schematic p.3	Follow chronological sequence	Pulled high with bidirectional data activity	DMM shows logic-high average; scope preferred	Bidirectional data bursts
7	RTC	RTC / CMOS supply	RTC source -> PCH/SoC	Schematic p.5	Follow chronological sequence	Typically near 3 V; board-specific	DMM DC	Flat DC
8	Always-On	3 V always-on rail	Standby regulator -> EC/PCH/logic	Schematic p.3	Follow chronological sequence	3.3 V nominal where this rail exists	DMM DC at inductor/output cap	Flat DC with low ripple
9	Always-On	5 V always-on rail	Standby regulator -> peripherals	Schematic p.2	Follow chronological sequence	5.0 V nominal where design provides always-on 5 V	DMM DC at inductor/output cap	Flat DC with low ripple
10	Always-On	1.8 V auxiliary rail	Standby regulator -> BIOS/PCH/logic	Schematic p.3	Follow chronological sequence	1.8 V nominal where used	DMM DC	Flat DC
11	EC / SIO	EC / SIO supply	Standby rail -> EC/SIO	Schematic p.5	Follow chronological sequence	Usually 3.3 V or design-specific auxiliary rail	DMM DC at EC decoupling capacitor	Flat DC
12	EC / SIO	EC reset	Reset circuit -> EC/SIO	Schematic p.41	Follow chronological sequence	Released to inactive logic level after EC supply is valid	DMM logic level	Clean release edge; no repetitive reset cycling
13	EC / SIO	32.768 kHz RTC / EC clock	Crystal/oscillator -> EC/PCH	Schematic p.5	Follow chronological sequence	Stable 32.768 kHz where external low-frequency clock is used	DMM not reliable; use scope	Stable low-amplitude sine/square waveform near 32.768 kHz
14	Power State	RSMRST#	EC/PCH resume-well logic	Schematic p.5	Follow chronological sequence	Inactive/high after resume-well prerequisites are satisfied	DMM logic level	Clean low-to-high transition during standby initialization
15	Power Button	PWRBTN# / ON-OFF# input	Power button -> EC	Schematic p.11	Follow chronological sequence	Normally high; clean active-low pulse on press	DMM min/max or scope	Single clean low pulse then returns high
16	Power Button	PBTN_OUT# / forwarded power button	EC -> PCH/SoC	Schematic p.5	Follow chronological sequence	Forwarded active-low pulse after EC accepts button request	DMM min/max or scope	Clean active-low pulse
17	Power Sequence	SLP_S5#	PCH/SoC -> EC/power logic	Schematic p.3	Follow chronological sequence	Deasserts/high when leaving S5; exact polarity/name platform-specific	DMM logic level	Step transition during power-on
18	Power Sequence	SLP_S4#	PCH/SoC -> EC/power logic	Schematic p.3	Follow chronological sequence	Deasserts/high when leaving S4	DMM logic level	Step transition
19	Power Sequence	SLP_S3#	PCH/SoC -> EC/power logic	Schematic p.3	Follow chronological sequence	Deasserts/high when entering S0	DMM logic level	Step transition
20	Memory	DDR VDD / VDDQ	Memory regulator -> DIMM/SoC	Schematic p.5	Follow chronological sequence	DDR generation-specific rail; verify schematic and memory generation	DMM DC at memory inductor	Flat DC; low ripple
21	Memory	DRAM reset	CPU/PCH/SoC -> memory	Schematic p.8	Follow chronological sequence	Released after memory power/clock prerequisites	DMM logic level	Clean reset release
22	CPU / SoC	VCCIO / CPU I/O rail	VR -> CPU/SoC	Schematic p.5	Follow chronological sequence	Platform-specific, commonly around 0.8-1.05 V on Intel generations	DMM DC at inductor	Flat DC; switching only at PWM nodes
23	CPU / SoC	VR_ON / CPU VR enable	EC/PCH -> CPU VR controller	Schematic p.5	Follow chronological sequence	Active before CPU core rail starts; logic level is board-specific	DMM logic level	Clean enable edge
24	CPU / SoC	CPU core rail	CPU VR -> processor core	Schematic p.56	Follow chronological sequence	VID-controlled dynamic voltage; do not use a single universal value	DMM DC at core inductor	Multiphase switching on switch nodes; DC on output
25	CPU / SoC	VR power-good	CPU VR -> EC/PCH	Schematic p.5	Follow chronological sequence	Asserted after CPU VR outputs are valid	DMM logic level	Clean assertion after core rail rises
26	CPU / SoC	SVID clock/data	CPU/SoC VR controller	Schematic p.15	Follow chronological sequence	High-speed digital activity when CPU negotiates VID; logic level platform-specific	DMM not diagnostic; use scope	Digital bursts during CPU VR initialization
27	Power Good	SYS_PWROK / ALL_SYS_PWRGD	PGOOD logic -> PCH/SoC	Schematic p.5	Follow chronological sequence	Asserted only after required S0 rails are valid	DMM logic level	Clean delayed assertion
28	Power Good	PCH_PWROK / SoC power-good	EC/PGOOD logic -> PCH/SoC	Schematic p.5	Follow chronological sequence	Asserted when platform power prerequisites are valid	DMM logic level	Clean delayed assertion
29	Reset	PLTRST#	PCH/SoC -> platform devices	Schematic p.5	Follow chronological sequence	Released/inactive after clocks and power-good conditions are satisfied	DMM logic level	Clean low-to-high release
30	BIOS / SPI	SPI_CS#	PCH/SoC/EC -> SPI flash	Schematic p.9	Follow chronological sequence	Idle high with access pulses during firmware reads	DMM not diagnostic; use scope	Chip-select pulse bursts during start-up
31	BIOS / SPI	SPI_CLK	PCH/SoC/EC -> SPI flash	Schematic p.6	Follow chronological sequence	Clock bursts during firmware access	DMM not diagnostic; use scope	High-frequency clock bursts
32	Display	eDP / LCD panel power	Load switch -> panel connector	Schematic p.6	Follow chronological sequence	Usually 3.3 V or platform-specific panel logic rail	DMM DC at panel connector/fuse	Flat DC
33	Display	eDP HPD	Panel -> GPU/PCH/SoC	Schematic p.6	Follow chronological sequence	Valid HPD logic state when panel is connected and powered	DMM logic level	Clean logic level/transition
34	Display	Backlight PWM	EC/PCH/GPU -> backlight driver	Schematic p.41	Follow chronological sequence	PWM duty cycle controls brightness; amplitude board-specific	DMM may show averaged voltage; scope preferred	PWM waveform with variable duty cycle

Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 34 checked

Checked	#	Signal / Rail	Failure Isolation Hint	Technician Notes
Checked	1	Adapter / DC-IN main railSchematic p.1	No rail: inspect adapter, jack, fuse, protection MOSFETs Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	2	ACOK / AC_PRESENTSchematic p.5	Missing: validate ACDET, charger supply, pull-up and charger IC Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	3	REGN / charger internal LDOSchematic p.52	Missing REGN with valid VCC may indicate charger IC fault Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	4	Battery positive / system battery railSchematic p.51	Abnormal: verify pack, connector, BATFET and charger path Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	5	Battery SMBus clockSchematic p.3	No activity: check pull-up rail, EC/charger, battery presence and bus shorts Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	6	Battery SMBus dataSchematic p.3	Stuck low/high: isolate battery/device and pull-up path Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	7	RTC / CMOS supplySchematic p.5	Missing RTC can block RSMRST# and standby sequencing Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	8	3 V always-on railSchematic p.3	Missing/shorted: inspect standby controller enable and rail resistance Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	9	5 V always-on railSchematic p.2	Missing: inspect enable, controller supply, MOSFETs and load short Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	10	1.8 V auxiliary railSchematic p.3	Missing may block flash/PCH/EC logic on newer platforms Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	11	EC / SIO supplySchematic p.5	Must be stable before reset release and power-button processing Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	12	EC resetSchematic p.41	Held reset: check EC VCC, reset supervisor/RC path and firmware conditions Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	13	32.768 kHz RTC / EC clockSchematic p.5	No clock: inspect crystal, load capacitors, supply and oscillator pins Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	14	RSMRST#Schematic p.5	Held low: trace RTC/standby rails, EC firmware, PCH/SoC prerequisites Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	15	PWRBTN# / ON-OFF# inputSchematic p.11	No pulse: button board, cable, ESD/filter path, pull-up or EC pin Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	16	PBTN_OUT# / forwarded power buttonSchematic p.5	Input pulse present but no output: EC firmware/state/prerequisite issue Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	17	SLP_S5#Schematic p.3	Missing: PCH/SoC not exiting soft-off; verify RSMRST#, clocks, firmware Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	18	SLP_S4#Schematic p.3	Missing: memory/suspend rails may not enable; trace earlier state signals Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	19	SLP_S3#Schematic p.3	Missing: system remains in sleep state; verify firmware/PCH prerequisites Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	20	DDR VDD / VDDQSchematic p.5	Missing: check enable from S4/S3 logic and resistance to ground Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	21	DRAM resetSchematic p.8	Held reset: trace memory rails, clocks, SYS_PWROK and platform reset sequence Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	22	VCCIO / CPU I/O railSchematic p.5	Missing: check enable, short and regulator controller Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	23	VR_ON / CPU VR enableSchematic p.5	Missing: EC/PCH has stopped sequence; inspect previous power-good signals Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	24	CPU core railSchematic p.56	0 V: verify VR_ON, controller supply, phase short and CPU condition Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	25	VR power-goodSchematic p.5	Missing: inspect VR feedback, phase faults, overcurrent/thermal protection Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	26	SVID clock/dataSchematic p.15	No activity with prerequisites valid: inspect CPU, VR controller, bus resistors Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	27	SYS_PWROK / ALL_SYS_PWRGDSchematic p.5	Missing: identify which upstream PGOOD/rail is absent Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	28	PCH_PWROK / SoC power-goodSchematic p.5	Missing: trace aggregate power-good logic and required rails Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	29	PLTRST#Schematic p.5	Held reset: check BIOS/SPI activity, clocks, PCH/SoC rails and PWROK Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	30	SPI_CS#Schematic p.9	No activity: sequence, reset, clock or controller may not have reached firmware fetch Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	31	SPI_CLKSchematic p.6	CS toggles but no clock: inspect controller/bus; no bus activity: trace sequence first Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	32	eDP / LCD panel powerSchematic p.6	Missing: check panel power enable, fuse/load switch and shorted panel/cable Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	33	eDP HPDSchematic p.6	Missing: panel/cable/connector power or HPD trace issue Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	34	Backlight PWMSchematic p.41	Enable present but no PWM: brightness/graphics/EC control path issue Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence

V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet

Adapter connectedANo successful-repair baseline yet

StandbyANo successful-repair baseline yet

Power-button pressANo successful-repair baseline yet

CPU initializationANo successful-repair baseline yet

BIOS activityANo successful-repair baseline yet

POSTANo successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for LA-J551P, LA-H105P.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

REFERENCE BOARD

LA-L181P

Revision: 1A

2/5 shared matching attributes

Same EC / SIOKB9052
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD

LA-J081P, LA-J091P

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 10
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD

LA-J371P

Revision: 1.0

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 10
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD

LA-J861P

Revision: 1A

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 10
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD

LA-J871P

Revision: 1.0

2/5 shared matching attributes

Same CPU generation / model seriesINTEL CORE GEN 10
Same platform / ODMCOMPAL

Open reference checklist →

REFERENCE BOARD