TCS Pune

19709 – Bench Power & Signal Checklist

Board-specific bench checklist derived from supplied schematic source(s) for 19709 SC. Only signals located in the supplied schematic text were added automatically; missing thresholds or values remain technician-verified rather than guessed.

V4.7 · REVISION SAFETY

19709 · Rev SC

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 19709Expert⏱ 60-180 minutes📋 5 steps

Compatible models: Mockingbird / Hellcat CML (DIS + UMA)

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify board/revision before using reference values.

🛠 Required Tools

  • Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required
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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): 19709 DIS.pdf | 19709 UMA.pdf

Board profile

Power & Control Architecture

Platform / ODMWistron
CPU / SoCIntel Comet Lake-U
PCH / ChipsetIntel PCH-LP
MemoryDDR4
EC / SIOMEC1515H-D0-I
ChargerISL9538C
BIOS / SPI8+16 MB SPI Flash ROM
USB-C / PDCYPD5126
GPUDIS and UMA variants
Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#StageSignal / RailFrom -> ToRefStateExpectedDMMOscilloscope
1DC InputAdapter / DC-IN main railInput connector / protection path19709 DIS p.43Follow chronological sequenceBoard-specific adapter/input voltage; verify source/PD contract and schematic.Measure DC to ground at the adapter/input protection path.Flat DC; investigate collapse or excessive ripple.
2ChargerACOK / ACINCharger -> EC/SMC19709 DIS p.44Follow chronological sequenceValid adapter-present logic state when the source is accepted; polarity is board/IC specific.Measure logic level and observe insertion/removal transition.Clean state transition on adapter insertion/removal.
3Always-On3V always-on / S5 railAlways-on 3V rail19709 DIS p.5Follow chronological sequenceNominal rail voltage indicated by schematic rail name; verify tolerance from source.Measure at rail coil/capacitor to ground.Clean startup and stable DC.
4Always-On5V always-on / S5 railAlways-on 5V rail19709 DIS p.35Follow chronological sequenceNominal rail voltage indicated by schematic rail name; verify tolerance from source.Measure at rail coil/capacitor to ground.Clean startup and stable DC.
5EC / SMCEC / SMC supplyEC/KBC/SMC power19709 DIS p.24Follow chronological sequenceBoard-specific EC/SMC supply must be valid and stable.Measure EC/SMC supply rails before expecting sequence outputs.Flat DC; no repeated collapse.
6EC / SMC32.768 kHz RTC / EC clockRTC / EC low-frequency clock19709 DIS p.24Follow chronological sequenceStable low-frequency oscillation where the board exposes/measures it.Oscilloscope with high-impedance probe; avoid loading crystal nodes.~32.768 kHz waveform when applicable.
7ResetRSMRST#EC/SMC/PCH reset path19709 DIS p.17Follow chronological sequenceMust release only after required standby power/clock conditions are met; polarity by signal suffix.Measure logic level and transition during standby sequence.Clean reset release.
8Power ButtonPWRBTN# / power switchButton -> EC/SMC/PCH19709 DIS p.17Follow chronological sequenceExpected active transition according to board polarity.Observe logic transition while pressing the button.Clean pulse on press/release.
9Sleep StateSLP_S5#PCH/SoC sleep state19709 DIS p.17Follow chronological sequenceMust transition according to the board power-state sequence.Measure logic state during attempted power-up.Clean state transition.
10Sleep StateSLP_S4#PCH/SoC sleep state19709 DIS p.17Follow chronological sequenceMust transition according to the board power-state sequence.Measure logic state during attempted power-up.Clean state transition.
11Sleep StateSLP_S3#PCH/SoC sleep state19709 DIS p.17Follow chronological sequenceMust transition before dependent S0 rails are expected.Measure logic state during attempted power-up.Clean state transition.
12MemoryMemory VDD / VDDQMemory power19709 DIS p.5Follow chronological sequenceNominal board-specific memory rail voltage for installed memory generation.Measure rail voltage at memory coil/capacitors.Stable DC with normal ramp.
13CPU / SoCVR_ON / CPU VR enableEC/SMC/SoC -> CPU VR19709 DIS p.46Follow chronological sequenceBoard-specific active logic state when CPU core power is requested.Measure enable logic at VR controller.Clean assertion before core rail rise.
14CPU / SoCCPU VCORECPU core regulator output19709 DIS p.46Follow chronological sequenceDynamic CPU core voltage; exact value depends on platform and operating state.Measure at CPU core inductor/output capacitors.Observe controlled ramp; scope ripple if unstable.
15CPU / SoCCPU VR power-good / VR_RDYCPU VR -> platform logic19709 DIS p.102Follow chronological sequenceAsserted only after the VR output is within regulation; exact polarity/name is board specific.Measure logic after core rail starts.Clean delayed assertion.
16CPU / SoCSVID clock/dataCPU/SoC VR controller19709 DIS p.7Follow chronological sequenceDigital activity during CPU voltage negotiation when supported.Use oscilloscope; DMM is not diagnostic for bus activity.Bursting clock/data activity.
17Power GoodSYS_PWROK / ALL_SYS_PWRGDAggregate power-good logic19709 DIS p.17Follow chronological sequenceAsserted only after required platform rails/power-good inputs are valid.Measure logic after required rails are stable.Clean delayed assertion.
18ResetPLTRST# / platform resetPCH/SoC -> platform devices19709 DIS p.17Follow chronological sequenceReleased only after clocks, firmware and power-good prerequisites are satisfied.Measure logic level and startup transition.Clean reset release.
19BIOS / SPIBIOS / SPI flash supplySPI flash supply19709 DIS p.2Follow chronological sequenceUse exact flash marking/datasheet; commonly 1.8 V or 3.3 V but never assume.Identify exact flash device first, then measure VCC.Stable DC.
20BIOS / SPISPI chip-selectController -> SPI flash19709 DIS p.18Follow chronological sequenceIdle/inactive with access pulses when firmware is being read.Oscilloscope during power-on/reset release.Chip-select pulse bursts.
21BIOS / SPISPI clockController -> SPI flash19709 DIS p.18Follow chronological sequenceClock bursts during flash access.Oscilloscope during firmware access.High-frequency clock bursts.
22DisplayLCD / eDP panel powerPanel power switch -> connector19709 DIS p.4Follow chronological sequenceBoard-specific panel logic supply as shown in schematic.Measure at panel connector/fuse/load switch.Stable DC after panel enable.
23DisplayeDP HPDPanel -> GPU/PCH/SoC19709 DIS p.4Follow chronological sequenceValid board-specific HPD state when panel is detected.Measure HPD logic with panel connected and powered.Clean logic level/transition.
24DisplayeDP AUXGPU/PCH/SoC panel19709 DIS p.4Follow chronological sequenceAUX transactions during panel detection/EDID/link setup.Use oscilloscope/differential method suitable for AUX; avoid loading the bus.Bidirectional AUX activity during display initialization.
25DisplayBacklight enableEC/PCH/GPU -> backlight path19709 DIS p.4Follow chronological sequenceBoard-specific active state after panel initialization.Measure enable logic when image/backlight should be active.Clean assertion.
26DisplayBacklight PWMEC/PCH/GPU -> backlight controller19709 DIS p.55Follow chronological sequencePWM activity when brightness is nonzero; exact frequency/duty is platform specific.Use oscilloscope; measure duty/frequency.Stable PWM waveform.
27BatteryBattery SMBusEC/charger battery19709 DIS p.24Follow chronological sequencePulled-high idle with transaction bursts when battery is queried.Use oscilloscope for clock/data activity; confirm pull-up rail.I2C/SMBus clock/data bursts.
28USB-C / PDUSB-C CC1 / CC2USB-C port -> PD controller19709 DIS p.2Follow chronological sequenceValid CC attachment/orientation state; exact voltage depends on source/sink role and Rp/Rd.Measure CC states according to Type-C/PD controller datasheet and port orientation.Observe attach/orientation changes.
29USB-C / PDPD negotiation / contractUSB-C PD controller19709 DIS p.2Follow chronological sequenceContract may be 5/9/15/20 V or PPS depending platform/source; do not assume 20 V.Verify 5 V default VBUS first, then observe negotiation and final contract.PD communication / VBUS transition when negotiation succeeds.
Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 29 checked
Checked#Signal / RailMeasuredObserved Waveform / LogicResultFailure Isolation HintTechnician Notes
1Adapter / DC-IN main rail19709 DIS p.43No input: inspect adapter/port, fuse, protection MOSFETs and shorted PBUS/system rail.
Additional readings
Technician evidence
2ACOK / ACIN19709 DIS p.44Missing: validate charger VCC, ACDET, source qualification and pull-up rail.
Additional readings
Technician evidence
33V always-on / S5 rail19709 DIS p.5Missing: inspect always-on controller enable/input, shorted load and power-good prerequisites.
Additional readings
Technician evidence
45V always-on / S5 rail19709 DIS p.35Missing: inspect always-on controller, enable, shorted load and input supply.
Additional readings
Technician evidence
5EC / SMC supply19709 DIS p.24Missing/unstable EC supply prevents power-button and sequencing logic.
Additional readings
Technician evidence
632.768 kHz RTC / EC clock19709 DIS p.24Absent clock: verify oscillator supply, crystal network and controller state.
Additional readings
Technician evidence
7RSMRST#19709 DIS p.17Held reset: work backward through always-on rails, RTC/clock, EC/SMC and PCH/SoC prerequisites.
Additional readings
Technician evidence
8PWRBTN# / power switch19709 DIS p.17No transition: inspect button, connector, pull-up and EC/SMC input path.
Additional readings
Technician evidence
9SLP_S5#19709 DIS p.17No transition: verify RSMRST#, firmware state, EC/SMC handshake and PCH/SoC prerequisites.
Additional readings
Technician evidence
10SLP_S4#19709 DIS p.17If missing, work backward through S5 prerequisites and firmware/EC handoff.
Additional readings
Technician evidence
11SLP_S3#19709 DIS p.17If missing, check upstream sleep-state logic, EC/SMC and platform power-good.
Additional readings
Technician evidence
12Memory VDD / VDDQ19709 DIS p.5Missing/low: inspect memory VR enable, short/load and power-state prerequisite.
Additional readings
Technician evidence
13VR_ON / CPU VR enable19709 DIS p.46Missing: do not condemn VR controller; trace upstream sleep/power-good/EC logic.
Additional readings
Technician evidence
14CPU VCORE19709 DIS p.460 V with valid enable: inspect VR input, controller, phases, current limit and rail resistance.
Additional readings
Technician evidence
15CPU VR power-good / VR_RDY19709 DIS p.102Missing: investigate VR feedback/phase faults/overcurrent and rail stability.
Additional readings
Technician evidence
16SVID clock/data19709 DIS p.7No activity with prerequisites valid: inspect CPU/VR bus path and controller supplies.
Additional readings
Technician evidence
17SYS_PWROK / ALL_SYS_PWRGD19709 DIS p.17Missing: identify the upstream rail or PGOOD that has not completed.
Additional readings
Technician evidence
18PLTRST# / platform reset19709 DIS p.17Held reset: verify firmware/SPI activity, clocks, SoC/PCH rails and PWROK chain.
Additional readings
Technician evidence
19BIOS / SPI flash supply19709 DIS p.2Wrong/missing supply: inspect flash power switch/rail and shorts before programming.
Additional readings
Technician evidence
20SPI chip-select19709 DIS p.18No activity: sequence may not have reached firmware fetch; verify upstream reset/clock/power first.
Additional readings
Technician evidence
21SPI clock19709 DIS p.18CS activity without clock suggests bus/controller issue; no bus activity may be upstream sequencing.
Additional readings
Technician evidence
22LCD / eDP panel power19709 DIS p.4Missing: inspect panel enable, fuse/load switch, shorted cable/panel and upstream display prerequisites.
Additional readings
Technician evidence
23eDP HPD19709 DIS p.4Missing: inspect panel power, cable/connector and HPD path.
Additional readings
Technician evidence
24eDP AUX19709 DIS p.4No AUX with power/HPD valid: inspect cable, panel and source path; do not infer GPU fault from one reading.
Additional readings
Technician evidence
25Backlight enable19709 DIS p.4Missing: inspect lid/Hall state, display initialization, firmware and control path.
Additional readings
Technician evidence
26Backlight PWM19709 DIS p.55Missing PWM with enable present: inspect brightness control source and firmware/EC path.
Additional readings
Technician evidence
27Battery SMBus19709 DIS p.24Stuck/no activity: inspect battery presence, pull-ups, bus shorts, EC/charger and pack.
Additional readings
Technician evidence
28USB-C CC1 / CC219709 DIS p.2Abnormal state: inspect port, ESD/protection, pull networks and PD controller supply before IC replacement.
Additional readings
Technician evidence
29PD negotiation / contract19709 DIS p.2No contract: verify CC state, controller supply, dead-battery path, firmware and source/cable compatibility.
Additional readings
Technician evidence
V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet
No successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for 19709.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.

V4.9 Diagnostic Timeline

Repair Timeline

Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.

    The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.

    GUIDED BIOS DIAGNOSTICS · V5.1

    BIOS / SPI Flash Diagnostic Record

    Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.

    Original BIOS dump

    The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.

    Repaired BIOS dump

    Stored as a separate attachment. Uploading it never modifies the original dump.

    Final diagnostic decision

    Is the problem solved?

    Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.

    V5.0 Repair Case Intelligence

    Board Repair Dashboard

    Aggregate repair patterns for 19709 · Rev SC. Historical patterns are references, not proof of the current fault.

    0Recorded repairs
    0.0%Solved
    Not enough timeline dataAverage diagnosis time
    0Rework cases

    Common symptoms

    No structured data yet.

    Frequently failed rails / signals

    No structured data yet.

    Frequently replaced / repaired ICs

    No structured data yet.

    Common root causes

    No structured data yet.

    Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.

    USB-C / PD DIAGNOSTICS · V5.2

    USB-C Power Delivery Diagnostic Record

    Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.

    USB-C port fault checklist

    Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.

    DISPLAY / NO-DISPLAY DIAGNOSTICS · V5.3

    Internal & External Display Diagnostic Record

    Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.

    Internal vs external display decision tree

    Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.

    Record the internal and external display results to show decision guidance.
    💰

    Estimated repair cost at TCS Pune

    ₹4,000 – ₹15,000

    Final price confirmed after free device inspection. Includes 6-month warranty.

    Get exact quote ↗
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