TCS Pune

D7 – Bench Power & Signal Checklist

Board-specific bench checklist derived from supplied schematic source(s) for D7 Rev A00. Only signals confidently located in the supplied source were added; undocumented thresholds remain technician-verified rather than guessed.

V4.7 · REVISION SAFETY

D7 · Rev A00

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

I verified the physical board revision is Rev A00.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 D7Expert⏱ 60-180 minutes📋 5 steps

Compatible models: Dell OptiPlex 3040 SFF

⚠ Safety: Disconnect battery/AC before resistance or diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Verify exact board/revision before using reference values.

🛠 Required Tools

Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required

0 / 5 done

1Confirm board identity and fault conditionRecord exact board code/revision, symptom, adapter/battery condition and current power state before measurements.⚠ Use the exact board revision; similar boards can use different rails, ICs or sequencing.
2Unpowered resistance / short checkWith all power removed, check input, always-on, memory and CPU/GPU rails for abnormal resistance before any injection.⚠ Low resistance on core rails can be normal. Never inject until safe voltage/current limits and topology are confirmed.
3Trace the chronological power sequenceFollow the board-specific rows in order and stop at the first missing prerequisite.⚠ A missing downstream signal is often a consequence, not the root cause.
4Capture dynamic signals where requiredUse a x10 probe and short ground connection for reset, SPI, PWM, CC/PD, eDP AUX and other dynamic signals.⚠ Avoid long probe ground leads on switching/high-speed nodes.
5Record repair and complete final QCAfter repair, repeat the failed stage and complete V5.9 final QC before marking solved.⚠ Do not publish solved until the original symptom is reproducibly cleared.

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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): OPTIPLEX 3040 d7- sff3_SFF 9 SFFa00_a_sch_1400_20150720.pdf

Board profile

Power & Control Architecture

Platform / ODMDell D7 / SFF3 Skylake

CPU / SoCIntel Skylake

MemoryDDR4

EC / SIONUVOTON NPCT650JAAYX

ChargerRT8237EZQW

BIOS / SPIMX25L12873FM2I-10G

Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#	Stage	Signal / Rail	From -> To	Ref	State	Expected	DMM	Oscilloscope
1	ATX / Standby	PS_ON#	SIO/PCH -> PSU enable	D7 schematic p.29	Follow chronological sequence	Board-specific active-low PSU enable transition.	Observe idle and power-on transition.	Clean assertion/deassertion.
2	ATX / Standby	ATX PWR_OK	PSU -> board power-good	D7 schematic p.5	Follow chronological sequence	Valid PSU power-good after main rails stabilize.	Measure logic transition after PS_ON#.	Clean assertion after stable rails.
3	Main Rails	+12V main rail	ATX/CPU/GPU input	D7 schematic p.5	Follow chronological sequence	Nominal 12 V-class rail; verify board-specific path.	Measure at ATX/EPS input and downstream fuse/MOSFET path.	Stable DC under startup/load.
4	Main Rails	+3.3V system rail	System 3.3 V rail	D7 schematic p.1	Follow chronological sequence	Nominal 3.3 V-class system rail.	Measure at regulator/output test point.	Stable DC.
5	EC / SMC	EC / KBC / SMC supply	EC/KBC/SMC power	D7 schematic p.1	Follow chronological sequence	Controller supply must be valid before sequence outputs are expected.	Measure controller supply rail(s).	Flat DC; no repeated collapse.
6	EC / SMC	32.768 kHz RTC / EC clock	RTC / EC low-frequency clock	D7 schematic p.25	Follow chronological sequence	Stable low-frequency oscillation where applicable.	Use high-impedance scope probe; avoid loading crystal nodes.	~32.768 kHz waveform where exposed.
7	Reset	RSMRST#	EC/PCH reset sequence	D7 schematic p.9	Follow chronological sequence	Board-specific deasserted state after resume-well prerequisites.	Measure logic state through power transition.	Clean assertion/deassertion.
8	Power Button	PWRBTN#	Button/EC -> PCH/SoC	D7 schematic p.9	Follow chronological sequence	Valid board-specific button transition when pressed.	Observe idle and pressed state.	Clean pulse/transition.
9	Sleep / Sequence	SLP_S5#	PCH/SoC -> power sequencing	D7 schematic p.24	Follow chronological sequence	Board-specific deassertion when leaving S5.	Measure during power-on sequence.	Clean transition.
10	Sleep / Sequence	SLP_S4#	PCH/SoC -> power sequencing	D7 schematic p.5	Follow chronological sequence	Board-specific deassertion when leaving S4.	Measure during power-on sequence.	Clean transition.
11	Sleep / Sequence	SLP_S3#	PCH/SoC -> main rails	D7 schematic p.5	Follow chronological sequence	Board-specific deassertion when entering S0.	Measure during power-on sequence.	Clean transition.
12	CPU / SoC VR	VCORE / CPU core rail	CPU/SoC core VR output	D7 schematic p.1	Follow chronological sequence	Dynamic low-voltage core rail; exact value depends on CPU state.	Measure at core inductors with suitable meter/scope.	Controlled ramp; switching activity under load.
13	Power Good	SYS_PWROK / ALL_SYS_PWRGD	System power-good chain	D7 schematic p.24	Follow chronological sequence	Valid board-specific power-good after required rails are stable.	Measure logic state after main rails rise.	Clean assertion.
14	Reset	PLTRST#	PCH/SoC -> platform devices	D7 schematic p.9	Follow chronological sequence	Deasserted platform reset after clocks, rails and power-good prerequisites.	Measure during startup.	Clean reset release.
15	BIOS / SPI	SPI chip select	Controller -> SPI flash	D7 schematic p.11	Follow chronological sequence	Idle/inactive with access pulses during firmware fetch.	Scope during power-on/reset release.	Chip-select pulse bursts.
16	BIOS / SPI	SPI clock	Controller -> SPI flash	D7 schematic p.22	Follow chronological sequence	Clock bursts during flash access.	Scope during firmware access.	High-frequency clock bursts.

Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 16 checked

Checked	#	Signal / Rail	Failure Isolation Hint	Technician Notes
Checked	1	PS_ON#D7 schematic p.29	No PS_ON#: check standby rails, SIO/EC state, power button and reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	2	ATX PWR_OKD7 schematic p.5	Missing PWR_OK: inspect PSU/main rails and excessive load. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	3	+12V main railD7 schematic p.5	Low/missing: inspect PSU, connector, protection path and shorts. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	4	+3.3V system railD7 schematic p.1	Missing: inspect source enable, regulator input and load. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	5	EC / KBC / SMC supplyD7 schematic p.1	Missing/unstable controller supply blocks power-button and sequencing logic. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	6	32.768 kHz RTC / EC clockD7 schematic p.25	Absent clock: verify oscillator supply, crystal network and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	7	RSMRST#D7 schematic p.9	Missing: check RTC/resume-well rails, EC/SMC state and upstream power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	8	PWRBTN#D7 schematic p.9	No transition: inspect button, EC path, pull-up and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	9	SLP_S5#D7 schematic p.24	Missing: diagnose upstream reset/firmware/power prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	10	SLP_S4#D7 schematic p.5	Missing: inspect prior sleep/reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	11	SLP_S3#D7 schematic p.5	Missing: inspect prior sleep/reset/firmware prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	12	VCORE / CPU core railD7 schematic p.1	Missing: inspect VR enable, controller supply, phases and SVID/control prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	13	SYS_PWROK / ALL_SYS_PWRGDD7 schematic p.24	Missing: find the first upstream rail or PGOOD that is absent. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	14	PLTRST#D7 schematic p.9	Missing: trace SYS_PWROK/VR_PWRGD/VR enable/sleep/reset prerequisites first. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	15	SPI chip selectD7 schematic p.11	No activity: verify sequence reached firmware fetch before suspecting the flash. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	16	SPI clockD7 schematic p.22	CS without clock suggests bus/controller path; no bus activity may be upstream sequence. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence

V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet

Adapter connectedANo successful-repair baseline yet

StandbyANo successful-repair baseline yet

Power-button pressANo successful-repair baseline yet

CPU initializationANo successful-repair baseline yet

BIOS activityANo successful-repair baseline yet

POSTANo successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for D7.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

V4.5 · SIMILAR BOARD / PLATFORM MATCHING

Reference Boards

Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.

REFERENCE BOARD