TCS Pune

6050A3217501 – Bench Power & Signal Checklist

Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.

V4.7 · REVISION SAFETY

6050A3217501 · Rev X01

Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.

I verified the physical board revision is Rev X01.

Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.

🔌 6050A3217501Expert⏱ 60-180 minutes📋 5 steps

Compatible models: EliteBook 840 G8

⚠ Safety: Disconnect battery before resistance/diode checks. Use current limiting for injection. Never inject voltage into an unknown rail until its safe voltage/current limit and isolation path are confirmed. Use a short ground spring for high-speed oscilloscope probing.

🛠 Required Tools

Digital multimeter Oscilloscope with x10 probe Bench power supply with current limit Thermal camera / freeze spray as required SPI programmer where firmware diagnosis is required

0 / 5 done

1Confirm board identity and fault conditionRecord exact board code/revision, reported symptom, adapter/battery condition, and current power state.⚠ Use the exact board revision; similar board codes can use different power ICs.
2Unpowered resistance / short checkWith all power removed, check main input and key rails for abnormal resistance to ground. Compare with known-good data where available.⚠ Low resistance on CPU/GPU core rails can be normal. Do not inject voltage until the rail topology and safe limit are confirmed.
3Trace the chronological power sequenceUse Table A in order. Stop at the first missing prerequisite and diagnose upstream.⚠ A missing downstream signal is often a consequence, not the root cause.
4Capture dynamic signals with oscilloscopeCapture power-button, sleep-state, reset, SPI and bus activity under the actual failure condition.⚠ Use a x10 probe and short ground connection; avoid loading crystal/high-speed nodes.
5Record repair and verify all functionsAfter repair, repeat the failed stage and complete final QC before marking solved.⚠ Do not mark solved until the original fault and final QC are verified.

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Schematic-derived bench record

Bench Manual & Source Coverage

Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.

Source PDF(s): HP_EliteBook_840_G8_Inventec_CORVETTE-6050A3217501-MB-AX2_Rev_X01.pdf

Board profile

Power & Control Architecture

Platform / ODMInventec / CORVETTE

CPU / SoCTiger Lake

MemoryDDR4

ChargerISL9241HRTZ

BIOS / SPIW25Q80DVZPIG

Table A

Chronological Power Sequence

Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.

#	Stage	Signal / Rail	From -> To	Ref	State	Expected	DMM	Oscilloscope
1	DC Input	Adapter / DC-IN main rail	Input connector / protection path	6050A3217501 schematic p.2	Follow chronological sequence	Board-specific adapter/input voltage; verify source and schematic.	Measure DC to ground at the input/protection path.	Flat DC; investigate collapse or excessive ripple.
2	Charger	ACOK / ACIN	Charger -> EC	6050A3217501 schematic p.7	Follow chronological sequence	Valid adapter-present logic state; polarity is board/IC specific.	Measure logic level and insertion/removal transition.	Clean state transition.
3	EC / SMC	EC / KBC / SMC supply	EC/KBC/SMC power	6050A3217501 schematic p.1	Follow chronological sequence	Controller supply must be valid before sequence outputs are expected.	Measure controller supply rail(s).	Flat DC; no repeated collapse.
4	EC / SMC	32.768 kHz RTC / EC clock	RTC / EC low-frequency clock	6050A3217501 schematic p.38	Follow chronological sequence	Stable low-frequency oscillation where applicable.	Use high-impedance scope probe; avoid loading crystal nodes.	~32.768 kHz waveform where exposed.
5	Reset	RSMRST#	EC/PCH reset sequence	6050A3217501 schematic p.2	Follow chronological sequence	Board-specific deasserted state after resume-well prerequisites.	Measure logic state through power transition.	Clean assertion/deassertion.
6	Power Button	PWRBTN#	Button/EC -> PCH/SoC	6050A3217501 schematic p.23	Follow chronological sequence	Valid board-specific button transition when pressed.	Observe idle and pressed state.	Clean pulse/transition.
7	Sleep State	SLP_S5#	PCH/SoC -> power sequence	6050A3217501 schematic p.28	Follow chronological sequence	Correct state transition for exit from S5.	Measure during power-button event.	Clean transition without repeated cycling.
8	Sleep State	SLP_S4#	PCH/SoC -> power sequence	6050A3217501 schematic p.6	Follow chronological sequence	Correct state transition for exit from S4.	Measure during startup.	Clean transition.
9	Sleep State	SLP_S3#	PCH/SoC -> power sequence	6050A3217501 schematic p.6	Follow chronological sequence	Correct state transition for exit from S3.	Measure during startup.	Clean transition.
10	Memory	Memory rail / VDDQ	Memory power	6050A3217501 schematic p.6	Follow chronological sequence	Board/memory-generation specific memory supply.	Measure at memory regulator output.	Stable DC after enable.
11	CPU VR	VR_ON / CPU VR enable	CPU VR enable	6050A3217501 schematic p.18	Follow chronological sequence	Enable must assert before CPU core rails rise.	Measure enable logic through startup.	Clean assertion.
12	CPU VR	CPU VCORE	CPU core regulator output	6050A3217501 schematic p.39	Follow chronological sequence	Dynamic CPU core voltage; exact value depends on CPU state.	Measure at CPU VR output coil.	Dynamic but stable under state/load changes.
13	Power Good	VR / system PGOOD	Regulators -> EC/PCH/SoC	6050A3217501 schematic p.6	Follow chronological sequence	Power-good signals should assert only after monitored rails are valid.	Measure logic and sequence timing.	Clean assertion after rail stabilization.
14	Reset	PLTRST#	PCH/SoC platform reset	6050A3217501 schematic p.28	Follow chronological sequence	Deasserts after required rails, clocks and power-good conditions are valid.	Measure during startup.	Clean reset release after prerequisites.
15	BIOS / SPI	SPI CS# / CLK / MOSI / MISO	PCH/SoC BIOS flash	6050A3217501 schematic p.29	Follow chronological sequence	Activity expected during firmware fetch; exact voltage depends on flash type.	Use scope on CLK/CS/data lines.	Burst activity during boot.
16	SMBus / I2C	SMBus / I2C activity	EC/charger/battery/system buses	6050A3217501 schematic p.2	Follow chronological sequence	Pulled-high bus with transaction activity where devices are queried.	Use scope; confirm idle level and bursts.	Digital clock/data bursts.
17	Display	eDP AUX / HPD	SoC/GPU -> panel	6050A3217501 schematic p.34	Follow chronological sequence	Board-specific eDP link-management activity after display power prerequisites.	Use scope and schematic-approved test points.	AUX bursts / HPD logic where applicable.
18	Backlight	BKL_EN / BKL_PWM	SoC/EC -> backlight	6050A3217501 schematic p.34	Follow chronological sequence	Enable/PWM should be present when image/backlight is commanded.	Measure logic/PWM at backlight control path.	Enable logic plus PWM waveform where applicable.
19	USB-C / PD	USB-C CC / PD negotiation	USB-C port -> PD controller	6050A3217501 schematic p.4	Follow chronological sequence	Observe board-specific CC state and PD negotiation; do not assume 20 V is always required.	Measure CC/VBUS with suitable tools and known-good adapter/cable.	CC communication / negotiated VBUS transition where supported.

Table B

Bench Reading & Fault Isolation

Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.

0 / 19 checked

Checked	#	Signal / Rail	Failure Isolation Hint	Technician Notes
Checked	1	Adapter / DC-IN main rail6050A3217501 schematic p.2	No input: inspect adapter, connector, fuse/protection MOSFETs and system-rail short. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	2	ACOK / ACIN6050A3217501 schematic p.7	Missing: verify charger VCC, ACDET/source qualification and pull-up rail. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	3	EC / KBC / SMC supply6050A3217501 schematic p.1	Missing/unstable controller supply blocks power-button and sequencing logic. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	4	32.768 kHz RTC / EC clock6050A3217501 schematic p.38	Absent clock: verify oscillator supply, crystal network and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	5	RSMRST#6050A3217501 schematic p.2	Missing: check RTC/resume-well rails, EC state and upstream power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	6	PWRBTN#6050A3217501 schematic p.23	No transition: inspect button, EC path, pull-up and controller state. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	7	SLP_S5#6050A3217501 schematic p.28	Missing transition: inspect prerequisites, EC/PCH state and reset/power-good. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	8	SLP_S4#6050A3217501 schematic p.6	Missing transition: trace upstream sleep/reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	9	SLP_S3#6050A3217501 schematic p.6	Missing transition: trace upstream sleep/reset prerequisites. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	10	Memory rail / VDDQ6050A3217501 schematic p.6	Missing: inspect memory regulator input, enable, short and PGOOD. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	11	VR_ON / CPU VR enable6050A3217501 schematic p.18	Missing: check SLP_S3#/S0 prerequisites and EC/PCH power-good chain. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	12	CPU VCORE6050A3217501 schematic p.39	Missing with valid enable: inspect VR input, controller, phases and load short. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	13	VR / system PGOOD6050A3217501 schematic p.6	Missing: identify which regulator/rail has not reached valid condition. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	14	PLTRST#6050A3217501 schematic p.28	Missing: work upstream through SYS_PWROK/VR PGOOD/sleep/reset chain. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	15	SPI CS# / CLK / MOSI / MISO6050A3217501 schematic p.29	No activity: verify flash supply/reset, PCH prerequisites, EC state and firmware path. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	16	SMBus / I2C activity6050A3217501 schematic p.2	Stuck bus: isolate pull-ups and devices; no activity may be a prerequisite/state issue. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	17	eDP AUX / HPD6050A3217501 schematic p.34	No activity: verify panel VCC, cable/connector, HPD, GPU/SoC state and firmware. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	18	BKL_EN / BKL_PWM6050A3217501 schematic p.34	Missing: inspect lid/hall state, panel detection, display sequencing and backlight power. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence
Checked	19	USB-C CC / PD negotiation6050A3217501 schematic p.4	No negotiation: check port, CC path, PD-controller supply, dead-battery path and charger handoff. Additional readings Resistance to ground (Ω)Diode mode (V)Current consumption	Technician evidence

V4.0 · BOARD COMPONENT INTELLIGENCE

Component Index

Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.

V4.3 Bench PSU Current Profile

Board Current Sequence

Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.

Current sequence: No readings yet

Adapter connectedANo successful-repair baseline yet

StandbyANo successful-repair baseline yet

Power-button pressANo successful-repair baseline yet

CPU initializationANo successful-repair baseline yet

BIOS activityANo successful-repair baseline yet

POSTANo successful-repair baseline yet

Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.

V4.4 Board Knowledge

Previous Solved Cases

Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.

Live match: Mark a bench signal FAIL to check previous solved cases for 6050A3217501.

No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.

Revision: 1.0