Board-specific bench checklist derived from supplied schematic source(s) for 820-01521 2.0.0. Only signals located in the supplied schematic text were added automatically; missing thresholds or values remain technician-verified rather than guessed.
Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.
Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.
Compatible models: J140 / X1032 MLB
Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): 820-01521 j140_mlb_bttf_051-04039_2.0.0.pdf
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
| # | Stage | Signal / Rail | From -> To | Ref | State | Expected | DMM | Oscilloscope |
|---|---|---|---|---|---|---|---|---|
| 1 | DC Input | Adapter / DC-IN main rail | Input connector / protection path | Schematic p.1 | Follow chronological sequence | Board-specific adapter/input voltage; verify source/PD contract and schematic. | Measure DC to ground at the adapter/input protection path. | Flat DC; investigate collapse or excessive ripple. |
| 2 | Always-On | 3V always-on / S5 rail | Always-on 3V rail | Schematic p.9 | Follow chronological sequence | Nominal rail voltage indicated by schematic rail name; verify tolerance from source. | Measure at rail coil/capacitor to ground. | Clean startup and stable DC. |
| 3 | EC / SMC | 32.768 kHz RTC / EC clock | RTC / EC low-frequency clock | Schematic p.65 | Follow chronological sequence | Stable low-frequency oscillation where the board exposes/measures it. | Oscilloscope with high-impedance probe; avoid loading crystal nodes. | ~32.768 kHz waveform when applicable. |
| 4 | Reset | RSMRST# | EC/SMC/PCH reset path | Schematic p.14 | Follow chronological sequence | Must release only after required standby power/clock conditions are met; polarity by signal suffix. | Measure logic level and transition during standby sequence. | Clean reset release. |
| 5 | Power Button | PWRBTN# / power switch | Button -> EC/SMC/PCH | Schematic p.2 | Follow chronological sequence | Expected active transition according to board polarity. | Observe logic transition while pressing the button. | Clean pulse on press/release. |
| 6 | Sleep State | SLP_S5# | PCH/SoC sleep state | Schematic p.15 | Follow chronological sequence | Must transition according to the board power-state sequence. | Measure logic state during attempted power-up. | Clean state transition. |
| 7 | Sleep State | SLP_S4# | PCH/SoC sleep state | Schematic p.15 | Follow chronological sequence | Must transition according to the board power-state sequence. | Measure logic state during attempted power-up. | Clean state transition. |
| 8 | Sleep State | SLP_S3# | PCH/SoC sleep state | Schematic p.5 | Follow chronological sequence | Must transition before dependent S0 rails are expected. | Measure logic state during attempted power-up. | Clean state transition. |
| 9 | Memory | Memory VDD / VDDQ | Memory power | Schematic p.1 | Follow chronological sequence | Nominal board-specific memory rail voltage for installed memory generation. | Measure rail voltage at memory coil/capacitors. | Stable DC with normal ramp. |
| 10 | CPU / SoC | VR_ON / CPU VR enable | EC/SMC/SoC -> CPU VR | Schematic p.59 | Follow chronological sequence | Board-specific active logic state when CPU core power is requested. | Measure enable logic at VR controller. | Clean assertion before core rail rise. |
| 11 | CPU / SoC | CPU VCORE | CPU core regulator output | Schematic p.1 | Follow chronological sequence | Dynamic CPU core voltage; exact value depends on platform and operating state. | Measure at CPU core inductor/output capacitors. | Observe controlled ramp; scope ripple if unstable. |
| 12 | Power Good | SYS_PWROK / ALL_SYS_PWRGD | Aggregate power-good logic | Schematic p.15 | Follow chronological sequence | Asserted only after required platform rails/power-good inputs are valid. | Measure logic after required rails are stable. | Clean delayed assertion. |
| 13 | Reset | PLTRST# / platform reset | PCH/SoC -> platform devices | Schematic p.5 | Follow chronological sequence | Released only after clocks, firmware and power-good prerequisites are satisfied. | Measure logic level and startup transition. | Clean reset release. |
| 14 | BIOS / SPI | BIOS / SPI flash supply | SPI flash supply | Schematic p.2 | Follow chronological sequence | Use exact flash marking/datasheet; commonly 1.8 V or 3.3 V but never assume. | Identify exact flash device first, then measure VCC. | Stable DC. |
| 15 | BIOS / SPI | SPI chip-select | Controller -> SPI flash | Schematic p.14 | Follow chronological sequence | Idle/inactive with access pulses when firmware is being read. | Oscilloscope during power-on/reset release. | Chip-select pulse bursts. |
| 16 | BIOS / SPI | SPI clock | Controller -> SPI flash | Schematic p.14 | Follow chronological sequence | Clock bursts during flash access. | Oscilloscope during firmware access. | High-frequency clock bursts. |
| 17 | Display | LCD / eDP panel power | Panel power switch -> connector | Schematic p.5 | Follow chronological sequence | Board-specific panel logic supply as shown in schematic. | Measure at panel connector/fuse/load switch. | Stable DC after panel enable. |
| 18 | Display | eDP HPD | Panel -> GPU/PCH/SoC | Schematic p.5 | Follow chronological sequence | Valid board-specific HPD state when panel is detected. | Measure HPD logic with panel connected and powered. | Clean logic level/transition. |
| 19 | Display | eDP AUX | GPU/PCH/SoC panel | Schematic p.5 | Follow chronological sequence | AUX transactions during panel detection/EDID/link setup. | Use oscilloscope/differential method suitable for AUX; avoid loading the bus. | Bidirectional AUX activity during display initialization. |
| 20 | Display | Backlight enable | EC/PCH/GPU -> backlight path | Schematic p.5 | Follow chronological sequence | Board-specific active state after panel initialization. | Measure enable logic when image/backlight should be active. | Clean assertion. |
| 21 | Display | Backlight PWM | EC/PCH/GPU -> backlight controller | Schematic p.5 | Follow chronological sequence | PWM activity when brightness is nonzero; exact frequency/duty is platform specific. | Use oscilloscope; measure duty/frequency. | Stable PWM waveform. |
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
| Checked | # | Signal / Rail | Measured | Observed Waveform / Logic | Result | Failure Isolation Hint | Technician Notes |
|---|---|---|---|---|---|---|---|
| 1 | Adapter / DC-IN main railSchematic p.1 | No input: inspect adapter/port, fuse, protection MOSFETs and shorted PBUS/system rail.Additional readings | Technician evidence | ||||
| 2 | 3V always-on / S5 railSchematic p.9 | Missing: inspect always-on controller enable/input, shorted load and power-good prerequisites.Additional readings | Technician evidence | ||||
| 3 | 32.768 kHz RTC / EC clockSchematic p.65 | Absent clock: verify oscillator supply, crystal network and controller state.Additional readings | Technician evidence | ||||
| 4 | RSMRST#Schematic p.14 | Held reset: work backward through always-on rails, RTC/clock, EC/SMC and PCH/SoC prerequisites.Additional readings | Technician evidence | ||||
| 5 | PWRBTN# / power switchSchematic p.2 | No transition: inspect button, connector, pull-up and EC/SMC input path.Additional readings | Technician evidence | ||||
| 6 | SLP_S5#Schematic p.15 | No transition: verify RSMRST#, firmware state, EC/SMC handshake and PCH/SoC prerequisites.Additional readings | Technician evidence | ||||
| 7 | SLP_S4#Schematic p.15 | If missing, work backward through S5 prerequisites and firmware/EC handoff.Additional readings | Technician evidence | ||||
| 8 | SLP_S3#Schematic p.5 | If missing, check upstream sleep-state logic, EC/SMC and platform power-good.Additional readings | Technician evidence | ||||
| 9 | Memory VDD / VDDQSchematic p.1 | Missing/low: inspect memory VR enable, short/load and power-state prerequisite.Additional readings | Technician evidence | ||||
| 10 | VR_ON / CPU VR enableSchematic p.59 | Missing: do not condemn VR controller; trace upstream sleep/power-good/EC logic.Additional readings | Technician evidence | ||||
| 11 | CPU VCORESchematic p.1 | 0 V with valid enable: inspect VR input, controller, phases, current limit and rail resistance.Additional readings | Technician evidence | ||||
| 12 | SYS_PWROK / ALL_SYS_PWRGDSchematic p.15 | Missing: identify the upstream rail or PGOOD that has not completed.Additional readings | Technician evidence | ||||
| 13 | PLTRST# / platform resetSchematic p.5 | Held reset: verify firmware/SPI activity, clocks, SoC/PCH rails and PWROK chain.Additional readings | Technician evidence | ||||
| 14 | BIOS / SPI flash supplySchematic p.2 | Wrong/missing supply: inspect flash power switch/rail and shorts before programming.Additional readings | Technician evidence | ||||
| 15 | SPI chip-selectSchematic p.14 | No activity: sequence may not have reached firmware fetch; verify upstream reset/clock/power first.Additional readings | Technician evidence | ||||
| 16 | SPI clockSchematic p.14 | CS activity without clock suggests bus/controller issue; no bus activity may be upstream sequencing.Additional readings | Technician evidence | ||||
| 17 | LCD / eDP panel powerSchematic p.5 | Missing: inspect panel enable, fuse/load switch, shorted cable/panel and upstream display prerequisites.Additional readings | Technician evidence | ||||
| 18 | eDP HPDSchematic p.5 | Missing: inspect panel power, cable/connector and HPD path.Additional readings | Technician evidence | ||||
| 19 | eDP AUXSchematic p.5 | No AUX with power/HPD valid: inspect cable, panel and source path; do not infer GPU fault from one reading.Additional readings | Technician evidence | ||||
| 20 | Backlight enableSchematic p.5 | Missing: inspect lid/Hall state, display initialization, firmware and control path.Additional readings | Technician evidence | ||||
| 21 | Backlight PWMSchematic p.5 | Missing PWM with enable present: inspect brightness control source and firmware/EC path.Additional readings | Technician evidence |
Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.
Embedded controller / system I/O sequencing
No matching components found.
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Revision: 1.0.0
Revision: A00
Revision: 1.0
Revision: 1.0
Revision: 1.0
Revision: 1.0
Revision: 1A
Revision: 1.0
Revision: 1.0
Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Stored as a separate attachment. Uploading it never modifies the original dump.
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
Aggregate repair patterns for 820-01521 · Rev 2.0.0. Historical patterns are references, not proof of the current fault.
No structured data yet.
No structured data yet.
No structured data yet.
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
₹4,000 – ₹15,000
Final price confirmed after free device inspection. Includes 6-month warranty.
