Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.
Verify the physical motherboard revision before using this checklist. Measurements, component values and power circuitry can change between revisions.
Only one published revision is currently stored for this board. Verify the silkscreen before proceeding.
Compatible models: Apple X502 MLB CATZ , 051-02265 .0
Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): Apple X502 MLB_CATZ 820-00875, 051-02265 r1.0.0.pdf
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
| # | Stage | Signal / Rail | From -> To | Ref | State | Expected | DMM | Oscilloscope |
|---|---|---|---|---|---|---|---|---|
| 1 | DC Input | Adapter / DC-IN main rail | Adapter/battery input path | Schematic p.1 | Follow chronological sequence | 19-20 V typical for barrel adapters; USB-C depends on PD contract | Measure to ground at input connector/fuse | Flat DC; inspect ripple only if unstable |
| 2 | DC Input | Input fuse - both sides | DC jack -> protection path | Schematic p.39 | Follow chronological sequence | Same voltage on both sides of input fuse | DMM DC at both fuse sides to ground; continuity with power removed | Flat DC |
| 3 | Charger | ACOK / AC_PRESENT | Charger -> EC/PCH | Schematic p.39 | Follow chronological sequence | Valid logic state when adapter accepted; commonly logic high | DMM logic level | Clean logic transition when adapter is inserted |
| 4 | Battery | Battery positive / system battery rail | Battery connector -> charger/system | Schematic p.39 | Follow chronological sequence | Pack voltage appropriate to cell count and state of charge | DMM DC at battery positive to pack ground | Flat DC; no excessive ripple |
| 5 | Battery | Battery SMBus clock | EC/charger battery | Schematic p.13 | Follow chronological sequence | Pulled high with communication activity when battery is queried | DMM shows logic-high average; scope preferred | Digital clock bursts |
| 6 | Battery | Battery SMBus data | EC/charger battery | Schematic p.13 | Follow chronological sequence | Pulled high with bidirectional data activity | DMM shows logic-high average; scope preferred | Bidirectional data bursts |
| 7 | RTC | RTC / CMOS supply | RTC source -> PCH/SoC | Schematic p.8 | Follow chronological sequence | Typically near 3 V; board-specific | DMM DC | Flat DC |
| 8 | EC / SIO | 32.768 kHz RTC / EC clock | Crystal/oscillator -> EC/PCH | Schematic p.15 | Follow chronological sequence | Stable 32.768 kHz where external low-frequency clock is used | DMM not reliable; use scope | Stable low-amplitude sine/square waveform near 32.768 kHz |
| 9 | Power Sequence | SLP_S3# | PCH/SoC -> EC/power logic | Schematic p.60 | Follow chronological sequence | Deasserts/high when entering S0 | DMM logic level | Step transition |
| 10 | Memory | DDR VDD / VDDQ | Memory regulator -> DIMM/SoC | Schematic p.8 | Follow chronological sequence | DDR generation-specific rail; verify schematic and memory generation | DMM DC at memory inductor | Flat DC; low ripple |
| 11 | CPU / SoC | VCCIO / CPU I/O rail | VR -> CPU/SoC | Schematic p.1 | Follow chronological sequence | Platform-specific, commonly around 0.8-1.05 V on Intel generations | DMM DC at inductor | Flat DC; switching only at PWM nodes |
| 12 | CPU / SoC | VCCSA / System Agent | VR -> CPU/SoC | Schematic p.1 | Follow chronological sequence | Platform-specific, commonly around 0.8-1.1 V | DMM DC at inductor | Flat DC |
| 13 | CPU / SoC | VR power-good | CPU VR -> EC/PCH | Schematic p.54 | Follow chronological sequence | Asserted after CPU VR outputs are valid | DMM logic level | Clean assertion after core rail rises |
| 14 | Power Good | SYS_PWROK / ALL_SYS_PWRGD | PGOOD logic -> PCH/SoC | Schematic p.14 | Follow chronological sequence | Asserted only after required S0 rails are valid | DMM logic level | Clean delayed assertion |
| 15 | Power Good | PCH_PWROK / SoC power-good | EC/PGOOD logic -> PCH/SoC | Schematic p.14 | Follow chronological sequence | Asserted when platform power prerequisites are valid | DMM logic level | Clean delayed assertion |
| 16 | BIOS / SPI | SPI_CLK | PCH/SoC/EC -> SPI flash | Schematic p.13 | Follow chronological sequence | Clock bursts during firmware access | DMM not diagnostic; use scope | High-frequency clock bursts |
| 17 | Display | eDP / LCD panel power | Load switch -> panel connector | Schematic p.5 | Follow chronological sequence | Usually 3.3 V or platform-specific panel logic rail | DMM DC at panel connector/fuse | Flat DC |
| 18 | Display | eDP HPD | Panel -> GPU/PCH/SoC | Schematic p.5 | Follow chronological sequence | Valid HPD logic state when panel is connected and powered | DMM logic level | Clean logic level/transition |
| 19 | Display | Backlight enable | EC/PCH/GPU -> panel/backlight | Schematic p.5 | Follow chronological sequence | Active logic level when backlight should turn on | DMM logic level | Clean assertion after panel power |
| 20 | Display | Backlight PWM | EC/PCH/GPU -> backlight driver | Schematic p.5 | Follow chronological sequence | PWM duty cycle controls brightness; amplitude board-specific | DMM may show averaged voltage; scope preferred | PWM waveform with variable duty cycle |
| 21 | USB-C / PD | USB-C VBUS | USB-C port -> system power path | Schematic p.29 | Follow chronological sequence | 5 V default; 9/15/20 V or other profiles after valid PD contract | DMM DC | Flat negotiated DC; scope for transients only |
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
| Checked | # | Signal / Rail | Measured | Observed Waveform / Logic | Result | Failure Isolation Hint | Technician Notes |
|---|---|---|---|---|---|---|---|
| 1 | Adapter / DC-IN main railSchematic p.1 | No rail: inspect adapter, jack, fuse, protection MOSFETsAdditional readings | Technician evidence | ||||
| 2 | Input fuse - both sidesSchematic p.39 | Drop/open: replace only after checking downstream shortAdditional readings | Technician evidence | ||||
| 3 | ACOK / AC_PRESENTSchematic p.39 | Missing: validate ACDET, charger supply, pull-up and charger ICAdditional readings | Technician evidence | ||||
| 4 | Battery positive / system battery railSchematic p.39 | Abnormal: verify pack, connector, BATFET and charger pathAdditional readings | Technician evidence | ||||
| 5 | Battery SMBus clockSchematic p.13 | No activity: check pull-up rail, EC/charger, battery presence and bus shortsAdditional readings | Technician evidence | ||||
| 6 | Battery SMBus dataSchematic p.13 | Stuck low/high: isolate battery/device and pull-up pathAdditional readings | Technician evidence | ||||
| 7 | RTC / CMOS supplySchematic p.8 | Missing RTC can block RSMRST# and standby sequencingAdditional readings | Technician evidence | ||||
| 8 | 32.768 kHz RTC / EC clockSchematic p.15 | No clock: inspect crystal, load capacitors, supply and oscillator pinsAdditional readings | Technician evidence | ||||
| 9 | SLP_S3#Schematic p.60 | Missing: system remains in sleep state; verify firmware/PCH prerequisitesAdditional readings | Technician evidence | ||||
| 10 | DDR VDD / VDDQSchematic p.8 | Missing: check enable from S4/S3 logic and resistance to groundAdditional readings | Technician evidence | ||||
| 11 | VCCIO / CPU I/O railSchematic p.1 | Missing: check enable, short and regulator controllerAdditional readings | Technician evidence | ||||
| 12 | VCCSA / System AgentSchematic p.1 | Missing: check enable/PGOOD and CPU rail sequencingAdditional readings | Technician evidence | ||||
| 13 | VR power-goodSchematic p.54 | Missing: inspect VR feedback, phase faults, overcurrent/thermal protectionAdditional readings | Technician evidence | ||||
| 14 | SYS_PWROK / ALL_SYS_PWRGDSchematic p.14 | Missing: identify which upstream PGOOD/rail is absentAdditional readings | Technician evidence | ||||
| 15 | PCH_PWROK / SoC power-goodSchematic p.14 | Missing: trace aggregate power-good logic and required railsAdditional readings | Technician evidence | ||||
| 16 | SPI_CLKSchematic p.13 | CS toggles but no clock: inspect controller/bus; no bus activity: trace sequence firstAdditional readings | Technician evidence | ||||
| 17 | eDP / LCD panel powerSchematic p.5 | Missing: check panel power enable, fuse/load switch and shorted panel/cableAdditional readings | Technician evidence | ||||
| 18 | eDP HPDSchematic p.5 | Missing: panel/cable/connector power or HPD trace issueAdditional readings | Technician evidence | ||||
| 19 | Backlight enableSchematic p.5 | Missing: lid/Hall state, graphics sequence, panel detection or firmwareAdditional readings | Technician evidence | ||||
| 20 | Backlight PWMSchematic p.5 | Enable present but no PWM: brightness/graphics/EC control path issueAdditional readings | Technician evidence | ||||
| 21 | USB-C VBUSSchematic p.29 | Stuck at 5 V/no VBUS: inspect CC negotiation, PD controller and power-path FETsAdditional readings | Technician evidence |
Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.
SPI firmware flash memory
USB-C configuration and power-delivery controller
No other published board checklist currently uses this exact stored IC part number.
No matching components found.
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Revision: 4.0.0
Revision: 1.0.0
Revision: A00
Revision: A00
Revision: 1A
Revision: 2.0
Revision: 1.0
Revision: 1.0
Revision: 1.0
Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Stored as a separate attachment. Uploading it never modifies the original dump.
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
Aggregate repair patterns for 820-00875 · Rev 1.0. Historical patterns are references, not proof of the current fault.
No structured data yet.
No structured data yet.
No structured data yet.
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
₹4,000 – ₹15,000
Final price confirmed after free device inspection. Includes 6-month warranty.
