TCS Pune

Sipeed Longan Nano GD32VF103

Development Board • RISC-V

Sipeed Longan Nano GD32VF103

Entry RISC-V board for bare-metal firmware and peripheral study.

Technical specifications

Manufacturer
GigaDevice / Sipeed
MCU / Part
GD32VF103CBT6
Architecture
32-bit RISC-V Bumblebee core
Logic voltage
3.3 V
Recommended input
5 V USB
GPIO limits
3.3 V; verify 5 V tolerance per pin
Flash
128 KB
RAM
32 KB
Clock
108 MHz
ADC
12-bit
DAC
2 × 12-bit
PWM / timers
Multiple 16-bit timers
Connectivity / buses
UART, I²C, SPI, CAN, USB FS
Programmer
DFU / RV-LINK
Debugger
JTAG/RV-LINK

Features and compatibility

Open official datasheet/documentation ↗
Deep reference

Architecture, electrical limits and engineering guidance

Exact MCU / SoC
GD32VF103CBT6
Maximum GPIO current
3.3 V; verify 5 V tolerance per pin
EEPROM / NVM
Use internal data flash/NVS/flash emulation where supported; include wear levelling and power-fail protection.
Interrupts / DMA
GPIO/peripheral interrupts are available. DMA capability is device-specific; confirm channels, request mapping and memory-access restrictions in the reference manual.
Sleep and power
Use the light/deep/standby modes offered by the device. Measure board current because regulators, LEDs and USB interfaces can dominate MCU sleep current.
Boot and programming
Confirm boot-mode pins before reset. Use the official bootloader/programmer and retain a recoverable debug/programming header.

Special and restricted pins

Reset, clock, debug, USB, crystal and analogue-reference pins have special electrical or boot functions. Avoid loading them until the boot sequence is understood.

Boot-strapping warnings

Check BOOT/RESET/programming pin truth tables before assigning peripherals; keep required pull resistors fitted.

I/O voltage warnings

3.3 V domain. Never exceed VDD + permitted injection limits; level-shift incompatible modules and share ground only where safe.

Memory map and registers

Start with the memory map: code flash, SRAM, peripheral registers and system/control space. Use vendor headers instead of hard-coded addresses, then study GPIO direction/output/input, clock-enable, interrupt and timer registers.

Board-selection guidance

Choose this device only after checking logic voltage, required interfaces, memory margin, timers/ADC resolution, debugging access, package availability and long-term tool support.

Common faults and troubleshooting

Not detected: verify data USB cable, driver, boot mode and target power. Upload failure: select the exact target and programmer. Unstable operation: inspect supply ripple, reset, clock and watchdog cause. Wrong readings: check reference voltage, grounding, pin multiplexing and calibration.

Interview and viva questions

What is the difference between an absolute maximum and an operating limit?

Absolute maximum prevents damage; reliable design stays within recommended operating conditions.

Why must peripheral clocks be enabled?

Many MCUs gate clocks to save power; registers may not operate until the peripheral clock is enabled.

Why preserve a debug interface?

It enables programming, breakpoints, fault inspection and production recovery.

What causes GPIO damage?

Over-voltage, excess source/sink current, negative injection, ESD or driving against another output.

Ready when you are

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