TCS Pune

ESP32-H2 DevKitM-1

Development Board • Espressif

ESP32-H2 DevKitM-1

Low-power RISC-V board for Bluetooth LE, Zigbee and Thread development.

Technical specifications

Manufacturer
Espressif
MCU / Part
ESP32-H2
Architecture
32-bit RISC-V
Logic voltage
3.3 V
Recommended input
5 V USB
GPIO limits
3.3 V only; not 5 V tolerant
Flash
External flash, board dependent
RAM
320 KB SRAM
Clock
96 MHz
ADC
12-bit SAR ADC
DAC
None
PWM / timers
LED PWM / motor PWM
Connectivity / buses
BLE 5, IEEE 802.15.4, UART, I²C, SPI, USB Serial/JTAG
Programmer
USB Serial/JTAG / UART bootloader
Debugger
Built-in USB JTAG

Features and compatibility

Open official datasheet/documentation ↗
Deep reference

Architecture, electrical limits and engineering guidance

Exact MCU / SoC
ESP32-H2
Maximum GPIO current
3.3 V only; not 5 V tolerant
EEPROM / NVM
Use internal data flash/NVS/flash emulation where supported; include wear levelling and power-fail protection.
Interrupts / DMA
GPIO/peripheral interrupts are available. DMA capability is device-specific; confirm channels, request mapping and memory-access restrictions in the reference manual.
Sleep and power
Use the light/deep/standby modes offered by the device. Measure board current because regulators, LEDs and USB interfaces can dominate MCU sleep current.
Boot and programming
Confirm boot-mode pins before reset. Use the official bootloader/programmer and retain a recoverable debug/programming header.

Special and restricted pins

Reset, clock, debug, USB, crystal and analogue-reference pins have special electrical or boot functions. Avoid loading them until the boot sequence is understood.

Boot-strapping warnings

Boot-strapping pins are sampled during reset. External pull-ups, pull-downs or connected modules must not force an invalid boot mode.

I/O voltage warnings

3.3 V domain. Never exceed VDD + permitted injection limits; level-shift incompatible modules and share ground only where safe.

Memory map and registers

Start with the memory map: code flash, SRAM, peripheral registers and system/control space. Use vendor headers instead of hard-coded addresses, then study GPIO direction/output/input, clock-enable, interrupt and timer registers.

Board-selection guidance

Choose this device only after checking logic voltage, required interfaces, memory margin, timers/ADC resolution, debugging access, package availability and long-term tool support.

Common faults and troubleshooting

Not detected: verify data USB cable, driver, boot mode and target power. Upload failure: select the exact target and programmer. Unstable operation: inspect supply ripple, reset, clock and watchdog cause. Wrong readings: check reference voltage, grounding, pin multiplexing and calibration.

Interview and viva questions

What is the difference between an absolute maximum and an operating limit?

Absolute maximum prevents damage; reliable design stays within recommended operating conditions.

Why must peripheral clocks be enabled?

Many MCUs gate clocks to save power; registers may not operate until the peripheral clock is enabled.

Why preserve a debug interface?

It enables programming, breakpoints, fault inspection and production recovery.

What causes GPIO damage?

Over-voltage, excess source/sink current, negative injection, ESD or driving against another output.

Ready when you are

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