Technical specifications
- Manufacturer
- Microchip
- MCU / Part
- PIC16F877A
- Architecture
- 8-bit PIC mid-range
- Logic voltage
- 2.0–5.5 V device dependent
- Recommended input
- Regulated VDD only
- GPIO limits
- Do not exceed VSS−0.3 V to VDD+0.3 V; observe port current limits
- Flash
- 8K × 14 words
- RAM
- 368 bytes
- Clock
- Up to 20 MHz
- ADC
- 8 channels, 10-bit
- DAC
- None
- PWM / timers
- 2 CCP/PWM channels
- Connectivity / buses
- USART, MSSP SPI/I²C, PSP
- Programmer
- PICkit / MPLAB Snap / ICD
- Debugger
- PICkit / MPLAB ICD
Pin reference
| Pin | Type | Main functions | Electrical note |
|---|
| MCLR/VPP | Reset/programming | Reset and programming voltage | Use recommended pull-up |
| OSC1/OSC2 | Clock | Crystal/external clock | Follow oscillator layout guidance |
| RA0–RA5 | GPIO/Analog | ADC/comparator/reference functions | Configure analog/digital mode |
| RC6/RC7 | UART | TX/RX | VDD logic levels |
| RC3–RC5 | SPI/I²C | SCK/SCL, SDA/SDI, SDO | Pull-ups for I²C |
| VDD/VSS | Power | Supply and ground pairs | Decouple every VDD pair |
Features and compatibility
EEPROM, timers, CCP, comparator
Verify the exact board revision and manufacturer documentation before wiring. Never apply 5 V to a 3.3 V-only GPIO.
Open official datasheet/documentation ↗Deep reference
Architecture, electrical limits and engineering guidance
- Exact MCU / SoC
- PIC16F877A
- Maximum GPIO current
- Do not exceed VSS−0.3 V to VDD+0.3 V; observe port current limits
- EEPROM / NVM
- Use internal data flash/NVS/flash emulation where supported; include wear levelling and power-fail protection.
- Interrupts / DMA
- GPIO/peripheral interrupts are available. DMA capability is device-specific; confirm channels, request mapping and memory-access restrictions in the reference manual.
- Sleep and power
- Use the light/deep/standby modes offered by the device. Measure board current because regulators, LEDs and USB interfaces can dominate MCU sleep current.
- Boot and programming
- Confirm boot-mode pins before reset. Use the official bootloader/programmer and retain a recoverable debug/programming header.
Special and restricted pins
Reset, clock, debug, USB, crystal and analogue-reference pins have special electrical or boot functions. Avoid loading them until the boot sequence is understood.
Boot-strapping warnings
Check BOOT/RESET/programming pin truth tables before assigning peripherals; keep required pull resistors fitted.
I/O voltage warnings
2.0–5.5 V device dependent domain. Never exceed VDD + permitted injection limits; level-shift incompatible modules and share ground only where safe.
Memory map and registers
Start with the memory map: code flash, SRAM, peripheral registers and system/control space. Use vendor headers instead of hard-coded addresses, then study GPIO direction/output/input, clock-enable, interrupt and timer registers.
Board-selection guidance
Choose this device only after checking logic voltage, required interfaces, memory margin, timers/ADC resolution, debugging access, package availability and long-term tool support.
Common faults and troubleshooting
Not detected: verify data USB cable, driver, boot mode and target power. Upload failure: select the exact target and programmer. Unstable operation: inspect supply ripple, reset, clock and watchdog cause. Wrong readings: check reference voltage, grounding, pin multiplexing and calibration.
Interview and viva questions
What is the difference between an absolute maximum and an operating limit?
Absolute maximum prevents damage; reliable design stays within recommended operating conditions.
Why must peripheral clocks be enabled?
Many MCUs gate clocks to save power; registers may not operate until the peripheral clock is enabled.
Why preserve a debug interface?
It enables programming, breakpoints, fault inspection and production recovery.
What causes GPIO damage?
Over-voltage, excess source/sink current, negative injection, ESD or driving against another output.
