Board-specific bench checklist derived from 1 supplied source PDF(s). Source coverage: High. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.
Compatible models: HP 15-ab / Pavilion 15 family
Source coverage: High. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): HP 15-ab225ur Quanta X12 X12A DAX12AMB6D0 PDF .pdf
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
| # | Stage | Signal / Rail | From -> To | Ref | State | Expected | DMM | Oscilloscope |
|---|---|---|---|---|---|---|---|---|
| 1 | DC Input | Adapter / DC-IN main rail | Input connector / protection path | DAX12AMB6D0 schematic p.30 | Follow chronological sequence | Board-specific adapter/input voltage; verify source and schematic. | Measure DC to ground at the input/protection path. | Flat DC; investigate collapse or excessive ripple. |
| 2 | Charger | ACDET | Charger adapter-detect divider | DAX12AMB6D0 schematic p.31 | Follow chronological sequence | Must be within the charger IC valid adapter-detect window; verify exact charger datasheet. | Measure DC at ACDET. | Stable analog level after adapter insertion. |
| 3 | Charger | ACOK / ACIN | Charger -> EC | DAX12AMB6D0 schematic p.29 | Follow chronological sequence | Valid adapter-present logic state; polarity is board/IC specific. | Measure logic level and insertion/removal transition. | Clean state transition. |
| 4 | Always-On | 3V always-on / S5 rail | Always-on 3V rail | DAX12AMB6D0 schematic p.4 | Follow chronological sequence | Nominal board-specific 3V-class always-on rail. | Measure at regulator output coil/capacitor. | Clean startup and stable DC. |
| 5 | Always-On | 5V always-on / S5 rail | Always-on 5V rail | DAX12AMB6D0 schematic p.13 | Follow chronological sequence | Nominal board-specific 5V-class always-on rail. | Measure at regulator output coil/capacitor. | Clean startup and stable DC. |
| 6 | EC / SMC | EC / KBC / SMC supply | EC/KBC/SMC power | DAX12AMB6D0 schematic p.1 | Follow chronological sequence | Controller supply must be valid before sequence outputs are expected. | Measure controller supply rail(s). | Flat DC; no repeated collapse. |
| 7 | EC / SMC | 32.768 kHz RTC / EC clock | RTC / EC low-frequency clock | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Stable low-frequency oscillation where applicable. | Use high-impedance scope probe; avoid loading crystal nodes. | ~32.768 kHz waveform where exposed. |
| 8 | Reset | RSMRST# | EC/PCH reset sequence | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Board-specific deasserted state after resume-well prerequisites. | Measure logic state through power transition. | Clean assertion/deassertion. |
| 9 | Power Button | PWRBTN# | Button/EC -> PCH/SoC | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Valid board-specific button transition when pressed. | Observe idle and pressed state. | Clean pulse/transition. |
| 10 | Sleep State | SLP_S5# | PCH/SoC -> power sequence | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Correct state transition for exit from S5. | Measure during power-button event. | Clean transition without repeated cycling. |
| 11 | Sleep State | SLP_S4# | PCH/SoC -> power sequence | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Correct state transition for exit from S4. | Measure during startup. | Clean transition. |
| 12 | Sleep State | SLP_S3# | PCH/SoC -> power sequence | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Correct state transition for exit from S3. | Measure during startup. | Clean transition. |
| 13 | Memory | Memory rail / VDDQ | Memory power | DAX12AMB6D0 schematic p.2 | Follow chronological sequence | Board/memory-generation specific memory supply. | Measure at memory regulator output. | Stable DC after enable. |
| 14 | CPU VR | VR_ON / CPU VR enable | CPU VR enable | DAX12AMB6D0 schematic p.4 | Follow chronological sequence | Enable must assert before CPU core rails rise. | Measure enable logic through startup. | Clean assertion. |
| 15 | CPU VR | CPU VCORE | CPU core regulator output | DAX12AMB6D0 schematic p.30 | Follow chronological sequence | Dynamic CPU core voltage; exact value depends on CPU state. | Measure at CPU VR output coil. | Dynamic but stable under state/load changes. |
| 16 | Power Good | VR / system PGOOD | Regulators -> EC/PCH/SoC | DAX12AMB6D0 schematic p.2 | Follow chronological sequence | Power-good signals should assert only after monitored rails are valid. | Measure logic and sequence timing. | Clean assertion after rail stabilization. |
| 17 | Reset | PLTRST# | PCH/SoC platform reset | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Deasserts after required rails, clocks and power-good conditions are valid. | Measure during startup. | Clean reset release after prerequisites. |
| 18 | BIOS / SPI | SPI CS# / CLK / MOSI / MISO | PCH/SoC BIOS flash | DAX12AMB6D0 schematic p.7 | Follow chronological sequence | Activity expected during firmware fetch; exact voltage depends on flash type. | Use scope on CLK/CS/data lines. | Burst activity during boot. |
| 19 | SMBus / I2C | SMBus / I2C activity | EC/charger/battery/system buses | DAX12AMB6D0 schematic p.8 | Follow chronological sequence | Pulled-high bus with transaction activity where devices are queried. | Use scope; confirm idle level and bursts. | Digital clock/data bursts. |
| 20 | Display | eDP AUX / HPD | SoC/GPU -> panel | DAX12AMB6D0 schematic p.2 | Follow chronological sequence | Board-specific eDP link-management activity after display power prerequisites. | Use scope and schematic-approved test points. | AUX bursts / HPD logic where applicable. |
| 21 | USB-C / PD | USB-C CC / PD negotiation | USB-C port -> PD controller | DAX12AMB6D0 schematic p.6 | Follow chronological sequence | Observe board-specific CC state and PD negotiation; do not assume 20 V is always required. | Measure CC/VBUS with suitable tools and known-good adapter/cable. | CC communication / negotiated VBUS transition where supported. |
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
| Checked | # | Signal / Rail | Measured | Observed Waveform / Logic | Result | Failure Isolation Hint | Technician Notes |
|---|---|---|---|---|---|---|---|
| 1 | Adapter / DC-IN main railDAX12AMB6D0 schematic p.30 | No input: inspect adapter, connector, fuse/protection MOSFETs and system-rail short.Additional readings | Technician evidence | ||||
| 2 | ACDETDAX12AMB6D0 schematic p.31 | Incorrect ACDET: inspect divider, charger supply and adapter path.Additional readings | Technician evidence | ||||
| 3 | ACOK / ACINDAX12AMB6D0 schematic p.29 | Missing: verify charger VCC, ACDET/source qualification and pull-up rail.Additional readings | Technician evidence | ||||
| 4 | 3V always-on / S5 railDAX12AMB6D0 schematic p.4 | Missing: inspect regulator input/enable, shorted load and prerequisite power-good.Additional readings | Technician evidence | ||||
| 5 | 5V always-on / S5 railDAX12AMB6D0 schematic p.13 | Missing: inspect regulator input/enable, shorted load and prerequisite power-good.Additional readings | Technician evidence | ||||
| 6 | EC / KBC / SMC supplyDAX12AMB6D0 schematic p.1 | Missing/unstable controller supply blocks power-button and sequencing logic.Additional readings | Technician evidence | ||||
| 7 | 32.768 kHz RTC / EC clockDAX12AMB6D0 schematic p.6 | Absent clock: verify oscillator supply, crystal network and controller state.Additional readings | Technician evidence | ||||
| 8 | RSMRST#DAX12AMB6D0 schematic p.6 | Missing: check RTC/resume-well rails, EC state and upstream power-good.Additional readings | Technician evidence | ||||
| 9 | PWRBTN#DAX12AMB6D0 schematic p.6 | No transition: inspect button, EC path, pull-up and controller state.Additional readings | Technician evidence | ||||
| 10 | SLP_S5#DAX12AMB6D0 schematic p.6 | Missing transition: inspect prerequisites, EC/PCH state and reset/power-good.Additional readings | Technician evidence | ||||
| 11 | SLP_S4#DAX12AMB6D0 schematic p.6 | Missing transition: trace upstream sleep/reset prerequisites.Additional readings | Technician evidence | ||||
| 12 | SLP_S3#DAX12AMB6D0 schematic p.6 | Missing transition: trace upstream sleep/reset prerequisites.Additional readings | Technician evidence | ||||
| 13 | Memory rail / VDDQDAX12AMB6D0 schematic p.2 | Missing: inspect memory regulator input, enable, short and PGOOD.Additional readings | Technician evidence | ||||
| 14 | VR_ON / CPU VR enableDAX12AMB6D0 schematic p.4 | Missing: check SLP_S3#/S0 prerequisites and EC/PCH power-good chain.Additional readings | Technician evidence | ||||
| 15 | CPU VCOREDAX12AMB6D0 schematic p.30 | Missing with valid enable: inspect VR input, controller, phases and load short.Additional readings | Technician evidence | ||||
| 16 | VR / system PGOODDAX12AMB6D0 schematic p.2 | Missing: identify which regulator/rail has not reached valid condition.Additional readings | Technician evidence | ||||
| 17 | PLTRST#DAX12AMB6D0 schematic p.6 | Missing: work upstream through SYS_PWROK/VR PGOOD/sleep/reset chain.Additional readings | Technician evidence | ||||
| 18 | SPI CS# / CLK / MOSI / MISODAX12AMB6D0 schematic p.7 | No activity: verify flash supply/reset, PCH prerequisites, EC state and firmware path.Additional readings | Technician evidence | ||||
| 19 | SMBus / I2C activityDAX12AMB6D0 schematic p.8 | Stuck bus: isolate pull-ups and devices; no activity may be a prerequisite/state issue.Additional readings | Technician evidence | ||||
| 20 | eDP AUX / HPDDAX12AMB6D0 schematic p.2 | No activity: verify panel VCC, cable/connector, HPD, GPU/SoC state and firmware.Additional readings | Technician evidence | ||||
| 21 | USB-C CC / PD negotiationDAX12AMB6D0 schematic p.6 | No negotiation: check port, CC path, PD-controller supply, dead-battery path and charger handoff.Additional readings | Technician evidence |
Select a board component to see its function, related rails/signals, enable and power-good dependencies, input/output path, matching checklist tests and identical fitted ICs found on other board checklists. Unknown values are left unknown rather than guessed.
SPI firmware flash memory
Battery charging / adapter power-path controller
Embedded controller / system I/O sequencing
No matching components found.
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Revision: 0B
Reference-board matches are discovery aids only. Missing information on this board is deliberately left unknown and is not filled from a similar board.
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Stored as a separate attachment. Uploading it never modifies the original dump.
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
Aggregate repair patterns for DAX12AMB6D0. Historical patterns are references, not proof of the current fault.
No structured data yet.
No structured data yet.
No structured data yet.
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
₹4,000 – ₹15,000
Final price confirmed after free device inspection. Includes 6-month warranty.
