| 1 | DC Input | Adapter / DC-IN main rail | Input connector / protection path | C223NA/C423NA/C523NA schematic p.30 | Follow chronological sequence | Board-specific adapter/input voltage; verify adapter or USB-C contract and schematic. | Measure DC to ground at the input/protection path. | Flat DC; investigate collapse or excessive ripple. |
| 2 | Charger | ACOK / ACIN | Charger -> EC/SMC | C223NA/C423NA/C523NA schematic p.30 | Follow chronological sequence | Valid adapter-present logic state; polarity is board/IC specific. | Measure logic level and insertion/removal transition. | Clean state transition. |
| 3 | EC / SMC | EC / KBC / SMC supply | EC/KBC/SMC power | C223NA/C423NA/C523NA schematic p.1 | Follow chronological sequence | Controller supply must be valid before sequence outputs are expected. | Measure controller supply rail(s). | Flat DC; no repeated collapse. |
| 4 | EC / SMC | 32.768 kHz RTC / EC clock | RTC / EC low-frequency clock | C223NA/C423NA/C523NA schematic p.15 | Follow chronological sequence | Stable low-frequency oscillation where applicable. | Use high-impedance scope probe; avoid loading crystal nodes. | ~32.768 kHz waveform where exposed. |
| 5 | Reset | RSMRST# | EC/PCH reset sequence | C223NA/C423NA/C523NA schematic p.13 | Follow chronological sequence | Board-specific deasserted state after resume-well prerequisites. | Measure logic state through power transition. | Clean assertion/deassertion. |
| 6 | Power Button | PWRBTN# | Button/EC -> PCH/SoC | C223NA/C423NA/C523NA schematic p.2 | Follow chronological sequence | Valid board-specific button transition when pressed. | Observe idle and pressed state. | Clean pulse/transition. |
| 7 | Sleep / Sequence | SLP_S4# | PCH/SoC -> power sequencing | C223NA/C423NA/C523NA schematic p.13 | Follow chronological sequence | Board-specific deassertion when leaving S4. | Measure during power-on sequence. | Clean transition. |
| 8 | Sleep / Sequence | SLP_S3# | PCH/SoC -> main rails | C223NA/C423NA/C523NA schematic p.13 | Follow chronological sequence | Board-specific deassertion when entering S0. | Measure during power-on sequence. | Clean transition. |
| 9 | Reset | PLTRST# | PCH/SoC -> platform devices | C223NA/C423NA/C523NA schematic p.13 | Follow chronological sequence | Deasserted platform reset after clocks, rails and power-good prerequisites. | Measure during startup. | Clean reset release. |
| 10 | BIOS / SPI | SPI chip select | Controller -> SPI flash | C223NA/C423NA/C523NA schematic p.12 | Follow chronological sequence | Idle/inactive with access pulses during firmware fetch. | Scope during power-on/reset release. | Chip-select pulse bursts. |
| 11 | BIOS / SPI | SPI clock | Controller -> SPI flash | C223NA/C423NA/C523NA schematic p.12 | Follow chronological sequence | Clock bursts during flash access. | Scope during firmware access. | High-frequency clock bursts. |
| 12 | Display | eDP HPD | Panel -> GPU/PCH/SoC | C223NA/C423NA/C523NA schematic p.6 | Follow chronological sequence | Valid board-specific HPD state when panel is detected. | Measure with panel connected and powered. | Clean logic level/transition. |
| 13 | Display | eDP AUX | GPU/PCH/SoC panel | C223NA/C423NA/C523NA schematic p.6 | Follow chronological sequence | AUX transactions during panel detection/EDID/link setup. | Use suitable scope/differential method; avoid loading the bus. | Bidirectional AUX activity. |
| 14 | Display | Backlight enable | EC/PCH/GPU -> backlight | C223NA/C423NA/C523NA schematic p.30 | Follow chronological sequence | Board-specific active state after panel initialization. | Measure enable logic when backlight should be active. | Clean assertion. |
| 15 | Display | Backlight PWM | EC/PCH/GPU -> backlight | C223NA/C423NA/C523NA schematic p.30 | Follow chronological sequence | PWM activity when brightness is nonzero; exact duty/frequency is platform specific. | Scope PWM and record duty/frequency. | Stable PWM waveform. |
| 16 | Battery / Bus | SMBus / I2C activity | EC/charger/battery bus | C223NA/C423NA/C523NA schematic p.1 | Follow chronological sequence | Pulled-high idle with transaction bursts when devices are queried. | Scope clock/data and confirm pull-up rail. | I2C/SMBus clock/data bursts. |
| 17 | USB-C / PD | USB-C CC1 / CC2 | USB-C port -> PD controller | C223NA/C423NA/C523NA schematic p.1 | Follow chronological sequence | Valid attachment/orientation state; exact voltage depends on Rp/Rd and role. | Measure CC states according to controller datasheet and port orientation. | Observe attach/orientation changes. |
| 18 | USB-C / PD | PD negotiation / contract | USB-C PD controller | C223NA/C423NA/C523NA schematic p.1 | Follow chronological sequence | Contract may be 5/9/15/20 V or PPS depending platform/source. | Verify default VBUS first, then observe negotiation and final contract. | PD communication / VBUS transition when negotiation succeeds. |