Original BIOS dump
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Search existing schematic component references and nets, then jump to the corresponding bench measurement. References are extracted from the checklist, not independently verified against the schematic.
8 measurement rows · 0 component references · 8 signal labels
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| Step | Signal / net | Component | Expected | Links |
|---|
Board-specific bench checklist derived from 2 supplied source PDF(s). Source coverage: Limited. Verify exact thresholds, pin numbers and rail tolerances against the source schematic and component datasheets before component replacement or voltage injection.
Source coverage: Limited. Values and thresholds must still be verified against the exact schematic/datasheet.
Source PDF(s): 820-02536.pdf | MLB 820-02536-09 (Silkscreen).pdf
Follow upstream to downstream. A missing later signal may simply be the result of an earlier missing prerequisite.
| # | Stage | Signal / Rail | From -> To | Ref | State | Expected | DMM | Oscilloscope |
|---|---|---|---|---|---|---|---|---|
| 1 | DC Input | Adapter / DC-IN main rail | Adapter/battery input path | Schematic p.23 | Follow chronological sequence | 19-20 V typical for barrel adapters; USB-C depends on PD contract | Measure to ground at input connector/fuse | Flat DC; inspect ripple only if unstable |
| 2 | Battery | Battery positive / system battery rail | Battery connector -> charger/system | Schematic p.23 | Follow chronological sequence | Pack voltage appropriate to cell count and state of charge | DMM DC at battery positive to pack ground | Flat DC; no excessive ripple |
| 3 | EC / SIO | 32.768 kHz RTC / EC clock | Crystal/oscillator -> EC/PCH | Schematic p.40 | Follow chronological sequence | Stable 32.768 kHz where external low-frequency clock is used | DMM not reliable; use scope | Stable low-amplitude sine/square waveform near 32.768 kHz |
| 4 | Memory | DDR VDD / VDDQ | Memory regulator -> DIMM/SoC | Schematic p.3 | Follow chronological sequence | DDR generation-specific rail; verify schematic and memory generation | DMM DC at memory inductor | Flat DC; low ripple |
| 5 | BIOS / SPI | SPI_CLK | PCH/SoC/EC -> SPI flash | Schematic p.23 | Follow chronological sequence | Clock bursts during firmware access | DMM not diagnostic; use scope | High-frequency clock bursts |
| 6 | Display | Backlight enable | EC/PCH/GPU -> panel/backlight | Schematic p.77 | Follow chronological sequence | Active logic level when backlight should turn on | DMM logic level | Clean assertion after panel power |
| 7 | Display | Backlight PWM | EC/PCH/GPU -> backlight driver | Schematic p.9 | Follow chronological sequence | PWM duty cycle controls brightness; amplitude board-specific | DMM may show averaged voltage; scope preferred | PWM waveform with variable duty cycle |
| 8 | USB-C / PD | USB-C VBUS | USB-C port -> system power path | Schematic p.28 | Follow chronological sequence | 5 V default; 9/15/20 V or other profiles after valid PD contract | DMM DC | Flat negotiated DC; scope for transients only |
Enter the actual DMM reading and scope/logic observation. Select PASS, FAIL or N/A, then tick Checked when that row is complete.
| Checked | # | Signal / Rail | Measured | Observed Waveform / Logic | Result | Failure Isolation Hint | Technician Notes |
|---|---|---|---|---|---|---|---|
| 1 | Adapter / DC-IN main railSchematic p.23 | No rail: inspect adapter, jack, fuse, protection MOSFETsAdditional readings | Technician evidence | ||||
| 2 | Battery positive / system battery railSchematic p.23 | Abnormal: verify pack, connector, BATFET and charger pathAdditional readings | Technician evidence | ||||
| 3 | 32.768 kHz RTC / EC clockSchematic p.40 | No clock: inspect crystal, load capacitors, supply and oscillator pinsAdditional readings | Technician evidence | ||||
| 4 | DDR VDD / VDDQSchematic p.3 | Missing: check enable from S4/S3 logic and resistance to groundAdditional readings | Technician evidence | ||||
| 5 | SPI_CLKSchematic p.23 | CS toggles but no clock: inspect controller/bus; no bus activity: trace sequence firstAdditional readings | Technician evidence | ||||
| 6 | Backlight enableSchematic p.77 | Missing: lid/Hall state, graphics sequence, panel detection or firmwareAdditional readings | Technician evidence | ||||
| 7 | Backlight PWMSchematic p.9 | Enable present but no PWM: brightness/graphics/EC control path issueAdditional readings | Technician evidence | ||||
| 8 | USB-C VBUSSchematic p.28 | Stuck at 5 V/no VBUS: inspect CC negotiation, PD controller and power-path FETsAdditional readings | Technician evidence |
Record current draw in amperes at each observable stage. Historical comparison uses successful repairs of this exact board checklist. A different reading is a clue, not a component diagnosis.
Tip: enter only stages you actually observed. For boards that never reach a later stage, leave that stage blank rather than entering a guessed value.
Historical cases are diagnostic references only. Confirm readings on the board in front of you before replacing parts.
No structured solved-repair knowledge has been collected for this board yet. New V4.4 solved cases will build it automatically.
Reference only: The boards below share one or more stored platform attributes with this motherboard. Their voltages, component locations, designators, sequence details and repair findings are not automatically treated as facts for the current board. Verify against the current board schematic, boardview and measurements before use.
Matching becomes available when published board records contain exact charger IC, EC/SIO, CPU model, CPU VR controller or Platform/ODM metadata.
Bench actions are recorded in sequence for training, QC and future troubleshooting. Signal result changes remain in history even after a failed stage later passes.
The final solved forum case receives the complete timeline for this bench session. Manual actions should describe what was actually done, not a suspected cause.
Record only measurements observed on this board. The workflow does not assume a flash voltage, logic level or firmware fault from a single reading.
The first uploaded original is locked to this diagnostic session and cannot be overwritten by this workflow.
Stored as a separate attachment. Uploading it never modifies the original dump.
Select two or more solved cases from this board. Comparison is for diagnostic reference only; different revisions can behave differently.
Complete the applicable checklist and bench rows first. If solved, the completed diagnostic flow is converted into a resolved Repair Forum post automatically.
Every item must be PASS, or N/A with a reason. Any FAIL reopens the repair and blocks the solved forum post.
This report uses the QC selections currently on this page. It does not mark the repair solved or modify existing reports.
Aggregate repair patterns for 820-02536. Historical patterns are references, not proof of the current fault.
No structured data yet.
No structured data yet.
No structured data yet.
No structured data yet.
Diagnosis time is calculated from V4.9 timeline evidence when available. Only server-recorded board-linked repair cases are counted; unsaved local bench sessions are excluded. Technician performance is never exposed on this board dashboard.
Record observed behavior on this board and adapter. Contract voltage and controller behavior vary by platform; this module does not assume that a higher-voltage PD contract must always be present.
Check only what was actually inspected. A failed item is a diagnostic clue, not an automatic component diagnosis.
Patterns are derived only from structured solved-case evidence for this board. Select a known failed signal below, or mark a bench row FAIL to open its matching history automatically.
Record board-specific observations. Missing display signals are clues only; expected voltage, polarity and timing must be verified from the schematic, panel specification or known-good board.
Complete the checks in order. The guidance below narrows the next area to inspect but does not declare a component faulty.
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Enter the actual reading and select PASS or FAIL in the bench table. The assistant follows the 820-02536 power sequence and V6.9 solved-case patterns to suggest what to measure next.
As you record actual readings, the next recommended test will appear here.
Diagnostic aid: recommendations are based on checklist order and recorded repair history. Verify the exact board revision, measurement method and power state. A suggested test is not a declaration that a component is faulty.
Board-specific firmware reference for 820-02536. Verify board revision, flash voltage/capacity, EC/ME requirements and checksum before programming.
No V7.3 known-good file is stored for this exact board/revision.
No V5.1 BIOS diagnostic dumps recorded for this board yet.
No BIOS/EC/ME solved-case reference has been identified for this exact board yet.
Safety: Compatibility is evidence, not permission to flash. Preserve the original dump and verify voltage, capacity, EC/ME region requirements, board revision and SHA-256.